Lines Matching refs:RK3588_DSU_CLKSEL_CON
182 .reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \
191 .reg = RK3588_DSU_CLKSEL_CON(0), \
200 .reg = RK3588_DSU_CLKSEL_CON(1), \
211 .reg = RK3588_DSU_CLKSEL_CON(2), \
218 .reg = RK3588_DSU_CLKSEL_CON(3), \
424 .core_reg[0] = RK3588_DSU_CLKSEL_CON(6),
427 .core_reg[1] = RK3588_DSU_CLKSEL_CON(6),
430 .core_reg[2] = RK3588_DSU_CLKSEL_CON(7),
433 .core_reg[3] = RK3588_DSU_CLKSEL_CON(7),
437 .mux_core_reg = RK3588_DSU_CLKSEL_CON(5),
841 RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS,
844 RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
847 RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
850 RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
853 RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
856 RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
859 RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
862 RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
865 RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
868 RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS,
871 RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS,
874 RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS,