Lines Matching refs:GATE
33 GATE(_id, cname, pname, f, o, b, gf)
804 GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0,
806 GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0,
808 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0,
810 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0,
812 GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL,
820 GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0,
822 GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
824 GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0,
832 GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0,
834 GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
836 GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0,
876 GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0,
878 GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL,
880 GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL,
882 GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED,
884 GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED,
886 GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0,
888 GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0,
898 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0,
900 GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0,
910 GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
923 GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0,
925 GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0,
929 GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0,
931 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0,
942 GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
953 GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
958 GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,
964 GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0,
974 GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0,
977 GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0,
987 GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0,
1002 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0,
1004 GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
1006 GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
1008 GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
1010 GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
1012 GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
1015 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0,
1020 GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1022 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0,
1027 GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1029 GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0,
1034 GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1037 GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0,
1039 GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0,
1044 GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0,
1046 GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0,
1048 GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0,
1050 GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0,
1052 GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0,
1054 GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0,
1056 GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0,
1058 GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0,
1060 GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0,
1062 GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0,
1064 GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0,
1066 GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0,
1069 GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0,
1071 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
1074 GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0,
1079 GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0,
1084 GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0,
1090 GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0,
1092 GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0,
1097 GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
1099 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
1101 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0,
1103 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL,
1106 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0,
1111 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0,
1116 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0,
1121 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0,
1127 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0,
1129 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0,
1131 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0,
1133 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0,
1135 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0,
1137 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0,
1139 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0,
1141 GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0,
1168 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0,
1170 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
1172 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
1174 GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
1176 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
1179 GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0,
1185 GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0,
1187 GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0,
1189 GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0,
1191 GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0,
1193 GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0,
1211 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED,
1213 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0,
1219 GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0,
1221 GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0,
1223 GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0,
1225 GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0,
1227 GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0,
1229 GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0,
1231 GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0,
1233 GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0,
1235 GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0,
1245 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
1254 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
1263 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
1272 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
1281 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
1290 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
1299 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
1308 GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0,
1317 GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0,
1337 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL,
1339 GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL,
1349 GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL,
1354 GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0,
1356 GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0,
1358 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
1363 GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0,
1365 GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0,
1367 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL,
1369 GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL,
1376 GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0,
1378 GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0,
1383 GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
1385 GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0,
1398 GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0,
1400 GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0,
1413 GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0,
1415 GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0,
1417 GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0,
1419 GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0,
1424 GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0,
1429 GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0,
1431 GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED,
1433 GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
1435 GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0,
1437 GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0,
1439 GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0,
1441 GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0,
1446 GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0,
1448 GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0,
1450 GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0,
1452 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
1462 GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
1470 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
1500 GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL,
1502 GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0,
1504 GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0,
1506 GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0,
1508 GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0,
1510 GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0,
1512 GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0,
1514 GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0,
1516 GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0,
1518 GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0,
1520 GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0,
1522 GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0,
1524 GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0,
1526 GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0,
1528 GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0,
1530 GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0,
1532 GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0,
1534 GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0,
1536 GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0,
1538 GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0,
1540 GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0,
1542 GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0,
1544 GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0,
1546 GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0,
1548 GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0,
1550 GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0,
1552 GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0,
1554 GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0,
1556 GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0,
1558 GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0,
1560 GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0,
1562 GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0,
1564 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0,
1566 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0,
1568 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0,
1570 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0,
1572 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0,
1574 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0,
1576 GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0,
1578 GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0,
1580 GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0,
1582 GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0,
1593 GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0,
1595 GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0,
1597 GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0,
1602 GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0,
1604 GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0,
1606 GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0,
1608 GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0,
1621 GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0,
1623 GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0,
1678 GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0,
1680 GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0,
1682 GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0,
1684 GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0,
1700 GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0,
1705 GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0,
1707 GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0,
1709 GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0,
1711 GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0,
1713 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0,
1715 GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0,
1717 GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0,
1722 GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0,
1724 GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0,
1729 GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0,
1745 GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
1747 GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
1769 GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0,
1771 GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0,
1773 GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0,
1775 GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0,
1777 GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0,
1779 GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0,
1781 GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0,
1783 GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0,
1785 GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0,
1787 GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0,
1792 GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0,
1794 GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0,
1802 GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0,
1804 GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0,
1806 GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0,
1808 GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0,
1813 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
1815 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
1834 GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0,
1836 GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0,
1838 GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0,
1840 GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0,
1842 GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0,
1844 GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0,
1846 GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0,
1848 GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0,
1850 GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0,
1852 GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
1862 GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0,
1872 GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0,
1882 GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0,
1884 GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0,
1894 GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0,
1896 GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0,
1947 GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0,
1949 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
1954 GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0,
1956 GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0,
1961 GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0,
1963 GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0,
1965 GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0,
1967 GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0,
1969 GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0,
1979 GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0,
1981 GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0,
1986 GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0,
1988 GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0,
1993 GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0,
1995 GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0,
1997 GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
1999 GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
2001 GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
2003 GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0,
2013 GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0,
2023 GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0,
2033 GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0,
2042 GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0,
2052 GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0,
2061 GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0,
2073 GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0,
2083 GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0,
2094 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
2096 GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0,
2098 GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0,
2100 GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0,
2102 GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0,
2104 GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0,
2106 GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0,
2108 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0,
2134 GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0,
2136 GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0,
2144 GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED,
2146 GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0,
2148 GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED,
2150 GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED,
2153 GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0,
2155 GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0,
2157 GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0,
2197 GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL,
2202 GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL,
2204 GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL,
2206 GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL,
2208 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
2213 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0,
2218 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0,
2228 GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
2238 GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
2242 GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL,
2244 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED,
2246 GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL,
2248 GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0,
2253 GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0,
2255 GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL,
2260 GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED,
2262 GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0,
2267 GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0,
2269 GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0,
2274 GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0,
2276 GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0,
2285 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
2287 GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0,
2289 GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0,
2306 GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
2308 GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
2310 GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
2312 GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0,
2315 GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0,
2317 GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0,
2319 GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0,
2321 GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0,
2323 GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0,
2325 GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0,
2327 GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0,
2329 GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0,
2331 GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0,
2333 GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0,
2335 GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0,
2337 GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0,
2339 GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0,
2341 GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0,
2343 GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0,
2345 GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0,
2347 GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0,
2349 GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0,
2351 GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0,
2353 GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0,
2355 GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0,
2357 GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0,
2359 GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0,
2361 GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0,
2363 GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0,
2365 GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0,
2367 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0,
2369 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0,
2371 GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0,
2373 GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0,
2375 GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0,
2377 GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0,
2379 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0,
2383 GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0,
2385 GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0,
2387 GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0,
2389 GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0,
2391 GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0,
2393 GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0,
2395 GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0,
2397 GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0,
2399 GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0,
2401 GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0,
2403 GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0,
2405 GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0,
2407 GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0,
2409 GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0,
2411 GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0,
2413 GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0,
2415 GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0,
2417 GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0,
2419 GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0,
2421 GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0,
2423 GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0,
2425 GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0,
2427 GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0,
2429 GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,