clk/rockchip/clk-rk3576.c

538 	GATE(CLK_GMAC0_RMII_CRU, "clk_gmac0_rmii_cru", "clk_cpll_div20", 0,
540 	GATE(CLK_GMAC1_RMII_CRU, "clk_gmac1_rmii_cru", "clk_cpll_div20", 0,
542 	GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
567 	GATE(HCLK_CAN0, "hclk_can0", "hclk_bus_root", 0,
572 	GATE(HCLK_CAN1, "hclk_can1", "hclk_bus_root", 0,
577 	GATE(CLK_KEY_SHIFT, "clk_key_shift", "xin24m", CLK_IS_CRITICAL,
579 	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0,
581 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_root", 0,
583 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0,
585 	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0,
587 	GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0,
589 	GATE(PCLK_I2C6, "pclk_i2c6", "pclk_bus_root", 0,
591 	GATE(PCLK_I2C7, "pclk_i2c7", "pclk_bus_root", 0,
593 	GATE(PCLK_I2C8, "pclk_i2c8", "pclk_bus_root", 0,
595 	GATE(PCLK_I2C9, "pclk_i2c9", "pclk_bus_root", 0,
597 	GATE(PCLK_WDT_BUSMCU, "pclk_wdt_busmcu", "pclk_bus_root", 0,
599 	GATE(TCLK_WDT_BUSMCU, "tclk_wdt_busmcu", "xin24m", 0,
601 	GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL,
630 	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_root", 0,
635 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", 0,
640 	GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
642 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0,
644 	GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0,
646 	GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0,
648 	GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,
650 	GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0,
652 	GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0,
654 	GATE(PCLK_UART8, "pclk_uart8", "pclk_bus_root", 0,
656 	GATE(PCLK_UART9, "pclk_uart9", "pclk_bus_root", 0,
658 	GATE(PCLK_UART10, "pclk_uart10", "pclk_bus_root", 0,
660 	GATE(PCLK_UART11, "pclk_uart11", "pclk_bus_root", 0,
695 	GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0,
697 	GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0,
699 	GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus_root", 0,
701 	GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus_root", 0,
703 	GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0,
720 	GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0,
722 	GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
724 	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0,
729 	GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
731 	GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_pvtm_clkout", 0,
733 	GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_bus_root", 0,
735 	GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_bus_root", 0,
740 	GATE(CLK_TIMER0, "clk_timer0", "clk_timer0_root", 0,
742 	GATE(CLK_TIMER1, "clk_timer1", "clk_timer0_root", 0,
744 	GATE(CLK_TIMER2, "clk_timer2", "clk_timer0_root", 0,
746 	GATE(CLK_TIMER3, "clk_timer3", "clk_timer0_root", 0,
748 	GATE(CLK_TIMER4, "clk_timer4", "clk_timer0_root", 0,
750 	GATE(CLK_TIMER5, "clk_timer5", "clk_timer0_root", 0,
752 	GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_bus_root", 0,
754 	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_root", 0,
756 	GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
758 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_root", 0,
760 	GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
762 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_root", 0,
764 	GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
766 	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus_root", 0,
768 	GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
770 	GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0,
772 	GATE(PCLK_DECOM, "pclk_decom", "pclk_bus_root", 0,
780 	GATE(CLK_TIMER6, "clk_timer6", "clk_timer1_root", 0,
788 	GATE(CLK_TIMER9, "clk_timer9", "clk_timer1_root", 0,
790 	GATE(CLK_TIMER10, "clk_timer10", "clk_timer1_root", 0,
792 	GATE(CLK_TIMER11, "clk_timer11", "clk_timer1_root", 0,
794 	GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
796 	GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
798 	GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0,
800 	GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0,
802 	GATE(HCLK_I3C0, "hclk_i3c0", "hclk_bus_root", 0,
804 	GATE(HCLK_I3C1, "hclk_i3c1", "hclk_bus_root", 0,
809 	GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus_cm0_root", 0,
814 	GATE(PCLK_PMU2, "pclk_pmu2", "pclk_bus_root", CLK_IS_CRITICAL,
816 	GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0,
821 	GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
823 	GATE(CLK_RC_PWM2, "clk_rc_pwm2", "clk_pvtm_clkout", 0,
843 	GATE(PCLK_CSIDPHY1, "pclk_csidphy1", "pclk_bus_root", 0,
868 	GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IGNORE_UNUSED,
870 	GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IGNORE_UNUSED,
872 	GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IGNORE_UNUSED,
874 	GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IGNORE_UNUSED,
881 	GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", CLK_IGNORE_UNUSED,
886 	GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_ddr_root", CLK_IS_CRITICAL,
891 	GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0,
893 	GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0,
895 	GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
897 	GATE(PCLK_WDT, "pclk_wdt", "pclk_ddr_root", 0,
899 	GATE(PCLK_TIMER, "pclk_timer", "pclk_ddr_root", 0,
909 	GATE(CLK_GPU, "clk_gpu", "clk_gpu_src_pre", 0,
922 	GATE(ACLK_RKNN0, "aclk_rknn0", "clk_rknn_dsu0", 0,
924 	GATE(ACLK_RKNN1, "aclk_rknn1", "clk_rknn_dsu0", 0,
929 	GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_nputop_root", 0,
934 	GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0,
936 	GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0,
938 	GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_nputop_root", 0,
940 	GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
942 	GATE(ACLK_RKNN_CBUF, "aclk_rknn_cbuf", "clk_rknn_dsu0", 0,
947 	GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0,
952 	GATE(HCLK_RKNN_CBUF, "hclk_rknn_cbuf", "hclk_rknn_root", 0,
965 	GATE(HCLK_FSPI, "hclk_fspi", "hclk_nvm_root", 0,
970 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm_root", 0,
972 	GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
977 	GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
990 	GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb_root", 0,
992 	GATE(CLK_REF_USB3OTG0, "clk_ref_usb3otg0", "xin24m", 0,
994 	GATE(CLK_SUSPEND_USB3OTG0, "clk_suspend_usb3otg0", "xin24m", 0,
996 	GATE(ACLK_MMU2, "aclk_mmu2", "aclk_usb_root", 0,
998 	GATE(ACLK_SLV_MMU2, "aclk_slv_mmu2", "aclk_usb_root", 0,
1000 	GATE(ACLK_UFS_SYS, "aclk_ufs_sys", "aclk_ufs_root", 0,
1013 	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0,
1018 	GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "aclk_rkvdec_root", 0,
1031 	GATE(HCLK_VEPU0, "hclk_vepu0", "hclk_vepu0_root", 0,
1033 	GATE(ACLK_VEPU0, "aclk_vepu0", "aclk_vepu0_root", 0,
1052 	GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
1054 	GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
1059 	GATE(CLK_ISP_CORE_MARVIN, "clk_isp_core_marvin", "clk_isp_core", 0,
1061 	GATE(CLK_ISP_CORE_VICAP, "clk_isp_core_vicap", "clk_isp_core", 0,
1063 	GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0,
1065 	GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0,
1067 	GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0,
1069 	GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0,
1071 	GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_isp_core", 0,
1073 	GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0,
1075 	GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0,
1077 	GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0,
1079 	GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0,
1081 	GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0,
1086 	GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0,
1097 	GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0,
1099 	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
1130 	GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_vo0_root", 0,
1132 	GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0_root", 0,
1134 	GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0,
1136 	GATE(CLK_TRNG0_SKP, "clk_trng0_skp", "aclk_hdcp0", 0,
1138 	GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vo0_root", 0,
1143 	GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo0_root", 0,
1148 	GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_vo0_root", 0,
1150 	GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo0_root", 0,
1152 	GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
1163 	GATE(HCLK_SAI5_8CH, "hclk_sai5_8ch", "hclk_vo0_root", 0,
1171 	GATE(HCLK_SAI6_8CH, "hclk_sai6_8ch", "hclk_vo0_root", 0,
1173 	GATE(HCLK_SPDIF_TX2, "hclk_spdif_tx2", "hclk_vo0_root", 0,
1178 	GATE(HCLK_SPDIF_RX2, "hclk_spdif_rx2", "hclk_vo0_root", 0,
1200 	GATE(HCLK_SAI8_8CH, "hclk_sai8_8ch", "hclk_vo1_root", 0,
1208 	GATE(HCLK_SAI7_8CH, "hclk_sai7_8ch", "hclk_vo1_root", 0,
1210 	GATE(HCLK_SPDIF_TX3, "hclk_spdif_tx3", "hclk_vo1_root", 0,
1212 	GATE(HCLK_SPDIF_TX4, "hclk_spdif_tx4", "hclk_vo1_root", 0,
1214 	GATE(HCLK_SPDIF_TX5, "hclk_spdif_tx5", "hclk_vo1_root", 0,
1222 	GATE(ACLK_DP0, "aclk_dp0", "aclk_vo1_root", 0,
1224 	GATE(PCLK_DP0, "pclk_dp0", "pclk_vo1_root", 0,
1226 	GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_vo1_root", 0,
1228 	GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1_root", 0,
1230 	GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0,
1232 	GATE(CLK_TRNG1_SKP, "clk_trng1_skp", "aclk_hdcp1", 0,
1234 	GATE(HCLK_SAI9_8CH, "hclk_sai9_8ch", "hclk_vo1_root", 0,
1265 	GATE(HCLK_RGA2E_0, "hclk_rga2e_0", "hclk_vpu_root", 0,
1267 	GATE(ACLK_RGA2E_0, "aclk_rga2e_0", "aclk_vpu_root", 0,
1272 	GATE(ACLK_JPEG, "aclk_jpeg", "aclk_jpeg_root", 0,
1274 	GATE(HCLK_JPEG, "hclk_jpeg", "hclk_vpu_root", 0,
1276 	GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vpu_root", 0,
1278 	GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vpu_mid_root", 0,
1283 	GATE(HCLK_RGA2E_1, "hclk_rga2e_1", "hclk_vpu_root", 0,
1285 	GATE(ACLK_RGA2E_1, "aclk_rga2e_1", "aclk_vpu_root", 0,
1295 	GATE(ACLK_EBC, "aclk_ebc", "aclk_vpu_low_root", 0,
1297 	GATE(HCLK_EBC, "hclk_ebc", "hclk_vpu_root", 0,
1310 	GATE(HCLK_VEPU1, "hclk_vepu1", "hclk_vepu1_root", 0,
1312 	GATE(ACLK_VEPU1, "aclk_vepu1", "aclk_vepu1_root", 0,
1325 	GATE(PCLK_PCIE0, "pclk_pcie0", "pclk_php_root", 0,
1327 	GATE(CLK_PCIE0_AUX, "clk_pcie0_aux", "xin24m", 0,
1329 	GATE(ACLK_PCIE0_MST, "aclk_pcie0_mst", "aclk_php_root", 0,
1331 	GATE(ACLK_PCIE0_SLV, "aclk_pcie0_slv", "aclk_php_root", 0,
1333 	GATE(ACLK_PCIE0_DBI, "aclk_pcie0_dbi", "aclk_php_root", 0,
1335 	GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_php_root", 0,
1337 	GATE(CLK_REF_USB3OTG1, "clk_ref_usb3otg1", "xin24m", 0,
1339 	GATE(CLK_SUSPEND_USB3OTG1, "clk_suspend_usb3otg1", "xin24m", 0,
1341 	GATE(ACLK_MMU0, "aclk_mmu0", "aclk_php_root", 0,
1343 	GATE(ACLK_SLV_MMU0, "aclk_slv_mmu0", "aclk_php_root", 0,
1345 	GATE(ACLK_MMU1, "aclk_mmu1", "aclk_php_root", 0,
1347 	GATE(ACLK_SLV_MMU1, "aclk_slv_mmu1", "aclk_php_root", 0,
1349 	GATE(PCLK_PCIE1, "pclk_pcie1", "pclk_php_root", 0,
1351 	GATE(CLK_PCIE1_AUX, "clk_pcie1_aux", "xin24m", 0,
1353 	GATE(ACLK_PCIE1_MST, "aclk_pcie1_mst", "aclk_php_root", 0,
1355 	GATE(ACLK_PCIE1_SLV, "aclk_pcie1_slv", "aclk_php_root", 0,
1357 	GATE(ACLK_PCIE1_DBI, "aclk_pcie1_dbi", "aclk_php_root", 0,
1365 	GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", CLK_IS_CRITICAL,
1367 	GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", CLK_IS_CRITICAL,
1369 	GATE(ACLK_SATA0, "aclk_sata0", "aclk_php_root", 0,
1371 	GATE(ACLK_SATA1, "aclk_sata1", "aclk_php_root", 0,
1378 	GATE(HCLK_ASRC_2CH_0, "hclk_asrc_2ch_0", "hclk_audio_root", 0,
1380 	GATE(HCLK_ASRC_2CH_1, "hclk_asrc_2ch_1", "hclk_audio_root", 0,
1382 	GATE(HCLK_ASRC_4CH_0, "hclk_asrc_4ch_0", "hclk_audio_root", 0,
1384 	GATE(HCLK_ASRC_4CH_1, "hclk_asrc_4ch_1", "hclk_audio_root", 0,
1404 	GATE(HCLK_SAI0_8CH, "hclk_sai0_8ch", "hclk_audio_root", 0,
1406 	GATE(HCLK_SPDIF_RX0, "hclk_spdif_rx0", "hclk_audio_root", 0,
1411 	GATE(HCLK_SPDIF_RX1, "hclk_spdif_rx1", "hclk_audio_root", 0,
1422 	GATE(HCLK_SAI1_8CH, "hclk_sai1_8ch", "hclk_audio_root", 0,
1430 	GATE(HCLK_SAI2_2CH, "hclk_sai2_2ch", "hclk_audio_root", 0,
1438 	GATE(HCLK_SAI3_2CH, "hclk_sai3_2ch", "hclk_audio_root", 0,
1446 	GATE(HCLK_SAI4_2CH, "hclk_sai4_2ch", "hclk_audio_root", 0,
1448 	GATE(HCLK_ACDCDIG_DSM, "hclk_acdcdig_dsm", "hclk_audio_root", 0,
1450 	GATE(MCLK_ACDCDIG_DSM, "mclk_acdcdig_dsm", "mclk_sai4_2ch", 0,
1455 	GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,
1457 	GATE(CLK_PDM1_OUT, "clk_pdm1_out", "clk_pdm1", 0,
1462 	GATE(HCLK_SPDIF_TX0, "hclk_spdif_tx0", "hclk_audio_root", 0,
1467 	GATE(HCLK_SPDIF_TX1, "hclk_spdif_tx1", "hclk_audio_root", 0,
1472 	GATE(CLK_SAI1_MCLKOUT, "clk_sai1_mclkout", "mclk_sai1_8ch", 0,
1474 	GATE(CLK_SAI2_MCLKOUT, "clk_sai2_mclkout", "mclk_sai2_2ch", 0,
1476 	GATE(CLK_SAI3_MCLKOUT, "clk_sai3_mclkout", "mclk_sai3_2ch", 0,
1478 	GATE(CLK_SAI4_MCLKOUT, "clk_sai4_mclkout", "mclk_sai4_2ch", 0,
1480 	GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0,
1493 	GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_sdgmac_root", 0,
1495 	GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_sdgmac_root", 0,
1497 	GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_sdgmac_root", 0,
1499 	GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_sdgmac_root", 0,
1504 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdgmac_root", 0,
1512 	GATE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", "clk_gmac1_ptp_ref_src", 0,
1514 	GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_src", 0,
1519 	GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_sdgmac_root", 0,
1524 	GATE(HCLK_FSPI1, "hclk_fspi1", "hclk_sdgmac_root", 0,
1529 	GATE(ACLK_DSMC, "aclk_dsmc", "aclk_dsmc_root", 0,
1531 	GATE(PCLK_DSMC, "pclk_dsmc", "pclk_sdgmac_root", 0,
1536 	GATE(HCLK_HSGPIO, "hclk_hsgpio", "hclk_sdgmac_root", 0,
1544 	GATE(ACLK_HSGPIO, "aclk_hsgpio", "aclk_sdgmac_root", 0,
1548 	GATE(PCLK_PHPPHY_ROOT, "pclk_phpphy_root", "pclk_bus_root", CLK_IS_CRITICAL,
1550 	GATE(PCLK_PCIE2_COMBOPHY0, "pclk_pcie2_combophy0", "pclk_phpphy_root", 0,
1552 	GATE(PCLK_PCIE2_COMBOPHY1, "pclk_pcie2_combophy1", "pclk_phpphy_root", 0,
1571 	GATE(CLK_200M_PMU_SRC, "clk_200m_pmu_src", "clk_gpll_div6", 0,
1587 	GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL,
1589 	GATE(PCLK_PMU1_ROOT, "pclk_pmu1_root", "pclk_pmu0_root", CLK_IS_CRITICAL,
1591 	GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu1_root", CLK_IS_CRITICAL,
1593 	GATE(CLK_PMU1, "clk_pmu1", "xin24m", CLK_IS_CRITICAL,
1595 	GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", CLK_IS_CRITICAL,
1597 	GATE(PCLK_HDPTX_APB, "pclk_hdptx_apb", "pclk_pmuphy_root", 0,
1599 	GATE(PCLK_MIPI_DCPHY, "pclk_mipi_dcphy", "pclk_pmuphy_root", 0,
1601 	GATE(PCLK_CSIDPHY, "pclk_csidphy", "pclk_pmuphy_root", 0,
1603 	GATE(PCLK_USBDPPHY, "pclk_usbdpphy", "pclk_pmuphy_root", 0,
1608 	GATE(CLK_USBDP_COMBO_PHY_IMMORTAL, "clk_usbdp_combo_phy_immortal", "xin24m", 0,
1610 	GATE(CLK_HDMITXHDP, "clk_hdmitxhdp", "xin24m", 0,
1612 	GATE(PCLK_MPHY, "pclk_mphy", "pclk_pmuphy_root", 0,
1616 	GATE(CLK_REF_UFS_CLKOUT, "clk_ref_ufs_clkout", "clk_ref_osc_mphy", 0,
1618 	GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", 0,
1623 	GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu1_root", 0,
1628 	GATE(PCLK_PMUTIMER, "pclk_pmutimer", "pclk_pmu1_root", 0,
1633 	GATE(CLK_PMUTIMER0, "clk_pmutimer0", "clk_pmutimer_root", 0,
1635 	GATE(CLK_PMUTIMER1, "clk_pmutimer1", "clk_pmutimer_root", 0,
1637 	GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu1_root", 0,
1642 	GATE(CLK_PMU1PWM_OSC, "clk_pmu1pwm_osc", "xin24m", 0,
1644 	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu1_root", 0,
1652 	GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0,
1654 	GATE(CLK_PDM0, "clk_pdm0", "clk_pdm0_src_top", 0,
1656 	GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0,
1658 	GATE(MCLK_PDM0, "mclk_pdm0", "mclk_pdm0_src_top", 0,
1660 	GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0,
1662 	GATE(CLK_PDM0_OUT, "clk_pdm0_out", "clk_pdm0", 0,
1667 	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
1672 	GATE(CLK_OSC0_PMU1, "clk_osc0_pmu1", "xin24m", CLK_IS_CRITICAL,
1674 	GATE(CLK_PMU1PWM_RC, "clk_pmu1pwm_rc", "clk_pvtm_clkout", 0,
1697 	GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_ns", 0,
1699 	GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_secure_ns", 0,
1701 	GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
1703 	GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_s", 0,
1705 	GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_s", 0,
1707 	GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto_s", 0,
1711 	GATE(CLK_VICAP_I0CLK, "clk_vicap_i0clk", "clk_csihost0_clkdata_i", 0,
1713 	GATE(CLK_VICAP_I1CLK, "clk_vicap_i1clk", "clk_csihost1_clkdata_i", 0,
1715 	GATE(CLK_VICAP_I2CLK, "clk_vicap_i2clk", "clk_csihost2_clkdata_i", 0,
1717 	GATE(CLK_VICAP_I3CLK, "clk_vicap_i3clk", "clk_csihost3_clkdata_i", 0,
1719 	GATE(CLK_VICAP_I4CLK, "clk_vicap_i4clk", "clk_csihost4_clkdata_i", 0,