clk/rockchip/clk-rk3399.c

109 PNAME(mux_pll_p)				= { "xin24m", "xin32k" };
111 PNAME(mux_armclkl_p)				= { "clk_core_l_lpll_src",
115 PNAME(mux_armclkb_p)				= { "clk_core_b_lpll_src",
119 PNAME(mux_ddrclk_p)				= { "clk_ddrc_lpll_src",
123 PNAME(mux_aclk_cci_p)				= { "cpll_aclk_cci_src",
127 PNAME(mux_cci_trace_p)				= { "cpll_cci_trace",
129 PNAME(mux_cs_p)					= { "cpll_cs", "gpll_cs",
131 PNAME(mux_aclk_perihp_p)			= { "cpll_aclk_perihp_src",
134 PNAME(mux_pll_src_cpll_gpll_p)			= { "cpll", "gpll" };
135 PNAME(mux_pll_src_cpll_gpll_npll_p)		= { "cpll", "gpll", "npll" };
136 PNAME(mux_pll_src_cpll_gpll_ppll_p)		= { "cpll", "gpll", "ppll" };
137 PNAME(mux_pll_src_cpll_gpll_upll_p)		= { "cpll", "gpll", "upll" };
138 PNAME(mux_pll_src_npll_cpll_gpll_p)		= { "npll", "cpll", "gpll" };
139 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p)	= { "cpll", "gpll", "npll",
141 PNAME(mux_pll_src_cpll_gpll_npll_24m_p)		= { "cpll", "gpll", "npll",
143 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p)	= { "cpll", "gpll", "npll",
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p)	= { "ppll", "cpll", "gpll",
147 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)	= { "cpll", "gpll", "npll",
149 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
152 PNAME(mux_pll_src_vpll_cpll_gpll_p)		= { "vpll", "cpll", "gpll" };
153 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)	= { "vpll", "cpll", "gpll",
155 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)		= { "vpll", "cpll", "gpll",
158 PNAME(mux_dclk_vop0_p)			= { "dclk_vop0_div",
160 PNAME(mux_dclk_vop1_p)			= { "dclk_vop1_div",
163 PNAME(mux_clk_cif_p)			= { "clk_cifout_src", "xin24m" };
165 PNAME(mux_pll_src_24m_usbphy480m_p)	= { "xin24m", "clk_usbphy_480m" };
166 PNAME(mux_pll_src_24m_pciephy_p)	= { "xin24m", "clk_pciephy_ref100m" };
167 PNAME(mux_pll_src_24m_32k_cpll_gpll_p)	= { "xin24m", "xin32k",
169 PNAME(mux_pciecore_cru_phy_p)		= { "clk_pcie_core_cru",
172 PNAME(mux_aclk_emmc_p)			= { "cpll_aclk_emmc_src",
175 PNAME(mux_aclk_perilp0_p)		= { "cpll_aclk_perilp0_src",
178 PNAME(mux_fclk_cm0s_p)			= { "cpll_fclk_cm0s_src",
181 PNAME(mux_hclk_perilp1_p)		= { "cpll_hclk_perilp1_src",
184 PNAME(mux_clk_testout1_p)		= { "clk_testout1_pll_src", "xin24m" };
185 PNAME(mux_clk_testout2_p)		= { "clk_testout2_pll_src", "xin24m" };
187 PNAME(mux_usbphy_480m_p)		= { "clk_usbphy0_480m_src",
189 PNAME(mux_aclk_gmac_p)			= { "cpll_aclk_gmac_src",
191 PNAME(mux_rmii_p)			= { "clk_gmac", "clkin_gmac" };
192 PNAME(mux_spdif_p)			= { "clk_spdif_div", "clk_spdif_frac",
194 PNAME(mux_i2s0_p)			= { "clk_i2s0_div", "clk_i2s0_frac",
196 PNAME(mux_i2s1_p)			= { "clk_i2s1_div", "clk_i2s1_frac",
198 PNAME(mux_i2s2_p)			= { "clk_i2s2_div", "clk_i2s2_frac",
200 PNAME(mux_i2sch_p)			= { "clk_i2s0", "clk_i2s1",
202 PNAME(mux_i2sout_p)			= { "clk_i2sout_src", "xin12m" };
204 PNAME(mux_uart0_p)	= { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
205 PNAME(mux_uart1_p)	= { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
206 PNAME(mux_uart2_p)	= { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
207 PNAME(mux_uart3_p)	= { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
210 PNAME(mux_ppll_24m_p)		= { "ppll", "xin24m" };
211 PNAME(mux_24m_ppll_p)		= { "xin24m", "ppll" };
212 PNAME(mux_fclk_cm0s_pmu_ppll_p)	= { "fclk_cm0s_pmu_ppll_src", "xin24m" };
213 PNAME(mux_wifi_pmu_p)		= { "clk_wifi_div", "clk_wifi_frac" };
214 PNAME(mux_uart4_pmu_p)		= { "clk_uart4_div", "clk_uart4_frac",
216 PNAME(mux_clk_testout2_2io_p)	= { "clk_testout2", "clk_32k_suspend_pmu" };