clk/rockchip/clk-rk3368.c

90 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
91 PNAME(mux_armclkb_p)		= { "apllb_core", "gpllb_core" };
92 PNAME(mux_armclkl_p)		= { "aplll_core", "gplll_core" };
93 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
94 PNAME(mux_cs_src_p)		= { "apllb_cs", "aplll_cs", "gpll_cs"};
95 PNAME(mux_aclk_bus_src_p)	= { "cpll_aclk_bus", "gpll_aclk_bus" };
97 PNAME(mux_pll_src_cpll_gpll_p)		= { "cpll", "gpll" };
98 PNAME(mux_pll_src_cpll_gpll_npll_p)	= { "cpll", "gpll", "npll" };
99 PNAME(mux_pll_src_npll_cpll_gpll_p)	= { "npll", "cpll", "gpll" };
100 PNAME(mux_pll_src_cpll_gpll_usb_p)	= { "cpll", "gpll", "usbphy_480m" };
101 PNAME(mux_pll_src_cpll_gpll_usb_usb_p)	= { "cpll", "gpll", "usbphy_480m",
103 PNAME(mux_pll_src_cpll_gpll_usb_npll_p)	= { "cpll", "gpll", "usbphy_480m",
105 PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
106 PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
109 PNAME(mux_i2s_8ch_pre_p)	= { "i2s_8ch_src", "i2s_8ch_frac",
111 PNAME(mux_i2s_8ch_clkout_p)	= { "i2s_8ch_pre", "xin12m" };
112 PNAME(mux_i2s_2ch_p)		= { "i2s_2ch_src", "i2s_2ch_frac",
114 PNAME(mux_spdif_8ch_p)		= { "spdif_8ch_pre", "spdif_8ch_frac",
116 PNAME(mux_edp_24m_p)		= { "xin24m", "dummy" };
117 PNAME(mux_vip_out_p)		= { "vip_src", "xin24m" };
118 PNAME(mux_usbphy480m_p)		= { "usbotg_out", "xin24m" };
119 PNAME(mux_hsic_usbphy480m_p)	= { "usbotg_out", "dummy" };
120 PNAME(mux_hsicphy480m_p)	= { "cpll", "gpll", "usbphy_480m" };
121 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
122 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
123 PNAME(mux_uart2_p)		= { "uart2_src", "xin24m" };
124 PNAME(mux_uart3_p)		= { "uart3_src", "uart3_frac", "xin24m" };
125 PNAME(mux_uart4_p)		= { "uart4_src", "uart4_frac", "xin24m" };
126 PNAME(mux_mac_p)		= { "mac_pll_src", "ext_gmac" };
127 PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "usbphy_480m", "xin24m" };