clk/rockchip/clk-rk3328.c

143 PNAME(mux_pll_p)		= { "xin24m" };
145 PNAME(mux_2plls_p)		= { "cpll", "gpll" };
146 PNAME(mux_gpll_cpll_p)		= { "gpll", "cpll" };
147 PNAME(mux_cpll_gpll_apll_p)	= { "cpll", "gpll", "apll" };
148 PNAME(mux_2plls_xin24m_p)	= { "cpll", "gpll", "xin24m" };
149 PNAME(mux_2plls_hdmiphy_p)	= { "cpll", "gpll",
151 PNAME(mux_4plls_p)		= { "cpll", "gpll",
154 PNAME(mux_2plls_u480m_p)	= { "cpll", "gpll",
156 PNAME(mux_2plls_24m_u480m_p)	= { "cpll", "gpll",
159 PNAME(mux_ddrphy_p)		= { "dpll", "apll", "cpll" };
160 PNAME(mux_armclk_p)		= { "apll_core",
164 PNAME(mux_hdmiphy_p)		= { "hdmi_phy", "xin24m" };
165 PNAME(mux_usb480m_p)		= { "usb480m_phy",
168 PNAME(mux_i2s0_p)		= { "clk_i2s0_div",
172 PNAME(mux_i2s1_p)		= { "clk_i2s1_div",
176 PNAME(mux_i2s2_p)		= { "clk_i2s2_div",
180 PNAME(mux_i2s1out_p)		= { "clk_i2s1", "xin12m"};
181 PNAME(mux_i2s2out_p)		= { "clk_i2s2", "xin12m" };
182 PNAME(mux_spdif_p)		= { "clk_spdif_div",
186 PNAME(mux_uart0_p)		= { "clk_uart0_div",
189 PNAME(mux_uart1_p)		= { "clk_uart1_div",
192 PNAME(mux_uart2_p)		= { "clk_uart2_div",
196 PNAME(mux_sclk_cif_p)		= { "clk_cif_src",
198 PNAME(mux_dclk_lcdc_p)		= { "hdmiphy",
200 PNAME(mux_aclk_peri_pre_p)	= { "cpll_peri",
203 PNAME(mux_ref_usb3otg_src_p)	= { "xin24m",
205 PNAME(mux_xin24m_32k_p)		= { "xin24m",
207 PNAME(mux_mac2io_src_p)		= { "clk_mac2io_src",
209 PNAME(mux_mac2phy_src_p)	= { "clk_mac2phy_src",
211 PNAME(mux_mac2io_ext_p)		= { "clk_mac2io",