clk/rockchip/clk-rk3328.c

21 	apll, dpll, cpll, gpll, npll,  enumerator
145 PNAME(mux_2plls_p)		= { "cpll", "gpll" };
146 PNAME(mux_gpll_cpll_p)		= { "gpll", "cpll" };
147 PNAME(mux_cpll_gpll_apll_p)	= { "cpll", "gpll", "apll" };
148 PNAME(mux_2plls_xin24m_p)	= { "cpll", "gpll", "xin24m" };
149 PNAME(mux_2plls_hdmiphy_p)	= { "cpll", "gpll",
151 PNAME(mux_4plls_p)		= { "cpll", "gpll",
154 PNAME(mux_2plls_u480m_p)	= { "cpll", "gpll",
156 PNAME(mux_2plls_24m_u480m_p)	= { "cpll", "gpll",
224 	[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
288 	GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
606 	GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,