clk/rockchip/clk-rk3188.c

19 	apll, cpll, dpll, gpll,  enumerator
201 PNAME(mux_pll_src_gpll_cpll_p)	= { "gpll", "cpll" };
202 PNAME(mux_pll_src_cpll_gpll_p)	= { "cpll", "gpll" };
203 PNAME(mux_aclk_cpu_p)		= { "apll", "gpll" };
212 PNAME(mux_mac_p)		= { "gpll", "dpll" };
222 	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
233 	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
280 	GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
298 	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
669 				    "gpll", "cpll" };
845 	clk2 = __clk_lookup("gpll");  in rk3188a_clk_init()
851 			pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",  in rk3188a_clk_init()
856 		pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",  in rk3188a_clk_init()