clk/rockchip/clk-px30.c

22 	gpll,  enumerator
142 PNAME(mux_4plls_p)		= { "gpll", "dummy_cpll", "usb480m", "npll" };
145 PNAME(mux_gpll_cpll_p)		= { "gpll", "dummy_cpll" };
146 PNAME(mux_gpll_npll_p)		= { "gpll", "npll" };
147 PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m"};
148 PNAME(mux_gpll_cpll_npll_p)		= { "gpll", "dummy_cpll", "npll" };
149 PNAME(mux_gpll_cpll_npll_xin24m_p)	= { "gpll", "dummy_cpll", "npll", "xin24m" };
150 PNAME(mux_gpll_xin24m_npll_p)		= { "gpll", "xin24m", "npll"};
162 PNAME(mux_uart_src_p)		= { "gpll", "xin24m", "usb480m", "npll" };
200 	[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll",  mux_pll_p, 0, PX30_PMU_PLL_CON(0),
280 	GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
334 	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
363 	COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED,
928 	COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0,
951 	COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0,
955 	COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0,