Lines Matching full:composite
384 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,
390 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
393 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
406 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,
415 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,
419 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
422 COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
431 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
442 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
448 COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,
468 COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0,
471 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
479 COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0,
492 COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
504 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
526 COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
545 COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0,
565 COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0,
589 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
599 COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
615 COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
631 COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
646 COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
661 COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,
674 COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0,
687 COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
700 COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
713 COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
726 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
729 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
732 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
735 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
738 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
741 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
744 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
747 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
785 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0,
788 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0,
935 COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0,