Lines Matching refs:GET_REG_OFFSET
60 #define GET_REG_OFFSET(val) ((val >> 20) & 0xfff) macro
170 u32 off = GET_REG_OFFSET(conf); in rzg2l_cpg_wait_clk_update_done()
183 u32 off = GET_REG_OFFSET(clk_hw_data->conf); in rzg2l_cpg_sd_clk_mux_notifier()
227 u32 off = GET_REG_OFFSET(clk_hw_data->conf); in rzg3s_cpg_div_clk_notifier()
291 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); in rzg3s_div_clk_recalc_rate()
317 u32 off = GET_REG_OFFSET(clk_hw_data->conf); in rzg3s_div_clk_set_rate()
419 base + GET_REG_OFFSET(core->conf), in rzg2l_cpg_div_clk_register()
428 base + GET_REG_OFFSET(core->conf), in rzg2l_cpg_div_clk_register()
448 priv->base + GET_REG_OFFSET(core->conf), in rzg2l_cpg_mux_clk_register()
463 u32 off = GET_REG_OFFSET(clk_hw_data->conf); in rzg2l_cpg_sd_clk_mux_set_parent()
493 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); in rzg2l_cpg_sd_clk_mux_get_parent()
736 return readl(priv->base + GET_REG_OFFSET(hwdata->conf)); in rzg2l_cpg_pll5_4_clk_mux_get_parent()