Lines Matching +full:core +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
48 * These are NOT valid for R-Car Gen1 and RZ/A1!
126 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
135 * @num_core_clks: Number of Core Clocks in clks[]
137 * @last_dt_core_clk: ID of the last Core Clock exported to DT
147 * @clks: Array containing all Core and Module Clocks
176 struct clk *clks[];
182 * struct mstp_clock - MSTP gating clock
183 * @hw: handle between common and hardware-specific interfaces
198 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_endisable()
199 unsigned int reg = clock->index / 32; in cpg_mstp_clock_endisable()
200 unsigned int bit = clock->index % 32; in cpg_mstp_clock_endisable()
201 struct device *dev = priv->dev; in cpg_mstp_clock_endisable()
207 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, in cpg_mstp_clock_endisable()
209 spin_lock_irqsave(&priv->rmw_lock, flags); in cpg_mstp_clock_endisable()
211 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
212 value = readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
217 writeb(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
220 readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
221 barrier_data(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
223 value = readl(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
228 writel(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
231 spin_unlock_irqrestore(&priv->rmw_lock, flags); in cpg_mstp_clock_endisable()
233 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable()
236 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], in cpg_mstp_clock_endisable()
240 priv->base + priv->control_regs[reg], bit); in cpg_mstp_clock_endisable()
258 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_is_enabled()
261 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
262 value = readb(priv->base + priv->control_regs[clock->index / 32]); in cpg_mstp_clock_is_enabled()
264 value = readl(priv->base + priv->status_regs[clock->index / 32]); in cpg_mstp_clock_is_enabled()
266 return !(value & BIT(clock->index % 32)); in cpg_mstp_clock_is_enabled()
276 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, in cpg_mssr_clk_src_twocell_get()
279 unsigned int clkidx = clkspec->args[1]; in cpg_mssr_clk_src_twocell_get()
281 struct device *dev = priv->dev; in cpg_mssr_clk_src_twocell_get()
284 struct clk *clk; in cpg_mssr_clk_src_twocell_get() local
287 switch (clkspec->args[0]) { in cpg_mssr_clk_src_twocell_get()
289 type = "core"; in cpg_mssr_clk_src_twocell_get()
290 if (clkidx > priv->last_dt_core_clk) { in cpg_mssr_clk_src_twocell_get()
293 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
295 clk = priv->clks[clkidx]; in cpg_mssr_clk_src_twocell_get()
300 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
302 range_check = 7 - (clkidx % 10); in cpg_mssr_clk_src_twocell_get()
305 range_check = 31 - (clkidx % 100); in cpg_mssr_clk_src_twocell_get()
307 if (range_check < 0 || idx >= priv->num_mod_clks) { in cpg_mssr_clk_src_twocell_get()
310 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
312 clk = priv->clks[priv->num_core_clks + idx]; in cpg_mssr_clk_src_twocell_get()
316 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); in cpg_mssr_clk_src_twocell_get()
317 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
320 if (IS_ERR(clk)) in cpg_mssr_clk_src_twocell_get()
322 PTR_ERR(clk)); in cpg_mssr_clk_src_twocell_get()
325 clkspec->args[0], clkspec->args[1], clk, in cpg_mssr_clk_src_twocell_get()
326 clk_get_rate(clk)); in cpg_mssr_clk_src_twocell_get()
327 return clk; in cpg_mssr_clk_src_twocell_get()
330 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, in cpg_mssr_register_core_clk() argument
334 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; in cpg_mssr_register_core_clk() local
335 struct device *dev = priv->dev; in cpg_mssr_register_core_clk()
336 unsigned int id = core->id, div = core->div; in cpg_mssr_register_core_clk()
339 WARN_DEBUG(id >= priv->num_core_clks); in cpg_mssr_register_core_clk()
340 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in cpg_mssr_register_core_clk()
342 if (!core->name) { in cpg_mssr_register_core_clk()
347 switch (core->type) { in cpg_mssr_register_core_clk()
349 clk = of_clk_get_by_name(priv->np, core->name); in cpg_mssr_register_core_clk()
355 WARN_DEBUG(core->parent >= priv->num_core_clks); in cpg_mssr_register_core_clk()
356 parent = priv->clks[core->parent]; in cpg_mssr_register_core_clk()
358 clk = parent; in cpg_mssr_register_core_clk()
364 if (core->type == CLK_TYPE_DIV6_RO) in cpg_mssr_register_core_clk()
366 div *= (readl(priv->base + core->offset) & 0x3f) + 1; in cpg_mssr_register_core_clk()
368 if (core->type == CLK_TYPE_DIV6P1) { in cpg_mssr_register_core_clk()
369 clk = cpg_div6_register(core->name, 1, &parent_name, in cpg_mssr_register_core_clk()
370 priv->base + core->offset, in cpg_mssr_register_core_clk()
371 &priv->notifiers); in cpg_mssr_register_core_clk()
373 clk = clk_register_fixed_factor(NULL, core->name, in cpg_mssr_register_core_clk()
375 core->mult, div); in cpg_mssr_register_core_clk()
380 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, in cpg_mssr_register_core_clk()
381 core->mult); in cpg_mssr_register_core_clk()
385 if (info->cpg_clk_register) in cpg_mssr_register_core_clk()
386 clk = info->cpg_clk_register(dev, core, info, in cpg_mssr_register_core_clk()
387 priv->clks, priv->base, in cpg_mssr_register_core_clk()
388 &priv->notifiers); in cpg_mssr_register_core_clk()
390 dev_err(dev, "%s has unsupported core clock type %u\n", in cpg_mssr_register_core_clk()
391 core->name, core->type); in cpg_mssr_register_core_clk()
395 if (IS_ERR_OR_NULL(clk)) in cpg_mssr_register_core_clk()
398 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); in cpg_mssr_register_core_clk()
399 priv->clks[id] = clk; in cpg_mssr_register_core_clk()
403 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", in cpg_mssr_register_core_clk()
404 core->name, PTR_ERR(clk)); in cpg_mssr_register_core_clk()
412 struct device *dev = priv->dev; in cpg_mssr_register_mod_clk()
413 unsigned int id = mod->id; in cpg_mssr_register_mod_clk()
415 struct clk *parent, *clk; in cpg_mssr_register_mod_clk() local
419 WARN_DEBUG(id < priv->num_core_clks); in cpg_mssr_register_mod_clk()
420 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
421 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
422 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in cpg_mssr_register_mod_clk()
424 if (!mod->name) { in cpg_mssr_register_mod_clk()
429 parent = priv->clks[mod->parent]; in cpg_mssr_register_mod_clk()
431 clk = parent; in cpg_mssr_register_mod_clk()
437 clk = ERR_PTR(-ENOMEM); in cpg_mssr_register_mod_clk()
441 init.name = mod->name; in cpg_mssr_register_mod_clk()
448 clock->index = id - priv->num_core_clks; in cpg_mssr_register_mod_clk()
449 clock->priv = priv; in cpg_mssr_register_mod_clk()
450 clock->hw.init = &init; in cpg_mssr_register_mod_clk()
452 for (i = 0; i < info->num_crit_mod_clks; i++) in cpg_mssr_register_mod_clk()
453 if (id == info->crit_mod_clks[i] && in cpg_mssr_register_mod_clk()
454 cpg_mstp_clock_is_enabled(&clock->hw)) { in cpg_mssr_register_mod_clk()
456 mod->name); in cpg_mssr_register_mod_clk()
466 for (i = 0; i < priv->num_reserved_ids; i++) { in cpg_mssr_register_mod_clk()
467 if (id == priv->reserved_ids[i]) { in cpg_mssr_register_mod_clk()
468 dev_info(dev, "Ignore Linux non-assigned mod (%s)\n", mod->name); in cpg_mssr_register_mod_clk()
474 clk = clk_register(NULL, &clock->hw); in cpg_mssr_register_mod_clk()
475 if (IS_ERR(clk)) in cpg_mssr_register_mod_clk()
478 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); in cpg_mssr_register_mod_clk()
479 priv->clks[id] = clk; in cpg_mssr_register_mod_clk()
480 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); in cpg_mssr_register_mod_clk()
485 mod->name, PTR_ERR(clk)); in cpg_mssr_register_mod_clk()
502 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) in cpg_mssr_is_pm_clk()
505 switch (clkspec->args[0]) { in cpg_mssr_is_pm_clk()
507 for (i = 0; i < pd->num_core_pm_clks; i++) in cpg_mssr_is_pm_clk()
508 if (clkspec->args[1] == pd->core_pm_clks[i]) in cpg_mssr_is_pm_clk()
523 struct device_node *np = dev->of_node; in cpg_mssr_attach_dev()
525 struct clk *clk; in cpg_mssr_attach_dev() local
531 return -EPROBE_DEFER; in cpg_mssr_attach_dev()
534 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, in cpg_mssr_attach_dev()
546 clk = of_clk_get_from_provider(&clkspec); in cpg_mssr_attach_dev()
549 if (IS_ERR(clk)) in cpg_mssr_attach_dev()
550 return PTR_ERR(clk); in cpg_mssr_attach_dev()
556 error = pm_clk_add_clk(dev, clk); in cpg_mssr_attach_dev()
565 clk_put(clk); in cpg_mssr_attach_dev()
584 struct device_node *np = dev->of_node; in cpg_mssr_add_clk_domain()
592 return -ENOMEM; in cpg_mssr_add_clk_domain()
594 pd->num_core_pm_clks = num_core_pm_clks; in cpg_mssr_add_clk_domain()
595 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); in cpg_mssr_add_clk_domain()
597 genpd = &pd->genpd; in cpg_mssr_add_clk_domain()
598 genpd->name = np->name; in cpg_mssr_add_clk_domain()
599 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | in cpg_mssr_add_clk_domain()
601 genpd->attach_dev = cpg_mssr_attach_dev; in cpg_mssr_add_clk_domain()
602 genpd->detach_dev = cpg_mssr_detach_dev; in cpg_mssr_add_clk_domain()
628 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); in cpg_mssr_reset()
631 writel(bitmask, priv->base + priv->reset_regs[reg]); in cpg_mssr_reset()
637 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); in cpg_mssr_reset()
649 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); in cpg_mssr_assert()
651 writel(bitmask, priv->base + priv->reset_regs[reg]); in cpg_mssr_assert()
663 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); in cpg_mssr_deassert()
665 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); in cpg_mssr_deassert()
677 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask); in cpg_mssr_status()
691 unsigned int unpacked = reset_spec->args[0]; in cpg_mssr_reset_xlate()
694 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { in cpg_mssr_reset_xlate()
695 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); in cpg_mssr_reset_xlate()
696 return -EINVAL; in cpg_mssr_reset_xlate()
704 priv->rcdev.ops = &cpg_mssr_reset_ops; in cpg_mssr_reset_controller_register()
705 priv->rcdev.of_node = priv->dev->of_node; in cpg_mssr_reset_controller_register()
706 priv->rcdev.of_reset_n_cells = 1; in cpg_mssr_reset_controller_register()
707 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; in cpg_mssr_reset_controller_register()
708 priv->rcdev.nr_resets = priv->num_mod_clks; in cpg_mssr_reset_controller_register()
709 return devm_reset_controller_register(priv->dev, &priv->rcdev); in cpg_mssr_reset_controller_register()
723 .compatible = "renesas,r7s9210-cpg-mssr",
729 .compatible = "renesas,r8a7742-cpg-mssr",
735 .compatible = "renesas,r8a7743-cpg-mssr",
740 .compatible = "renesas,r8a7744-cpg-mssr",
746 .compatible = "renesas,r8a7745-cpg-mssr",
752 .compatible = "renesas,r8a77470-cpg-mssr",
758 .compatible = "renesas,r8a774a1-cpg-mssr",
764 .compatible = "renesas,r8a774b1-cpg-mssr",
770 .compatible = "renesas,r8a774c0-cpg-mssr",
776 .compatible = "renesas,r8a774e1-cpg-mssr",
782 .compatible = "renesas,r8a7790-cpg-mssr",
788 .compatible = "renesas,r8a7791-cpg-mssr",
791 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
793 .compatible = "renesas,r8a7793-cpg-mssr",
799 .compatible = "renesas,r8a7792-cpg-mssr",
805 .compatible = "renesas,r8a7794-cpg-mssr",
811 .compatible = "renesas,r8a7795-cpg-mssr",
817 .compatible = "renesas,r8a7796-cpg-mssr",
823 .compatible = "renesas,r8a77961-cpg-mssr",
829 .compatible = "renesas,r8a77965-cpg-mssr",
835 .compatible = "renesas,r8a77970-cpg-mssr",
841 .compatible = "renesas,r8a77980-cpg-mssr",
847 .compatible = "renesas,r8a77990-cpg-mssr",
853 .compatible = "renesas,r8a77995-cpg-mssr",
859 .compatible = "renesas,r8a779a0-cpg-mssr",
865 .compatible = "renesas,r8a779f0-cpg-mssr",
871 .compatible = "renesas,r8a779g0-cpg-mssr",
877 .compatible = "renesas,r8a779h0-cpg-mssr",
900 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_suspend_noirq()
901 if (priv->smstpcr_saved[reg].mask) in cpg_mssr_suspend_noirq()
902 priv->smstpcr_saved[reg].val = in cpg_mssr_suspend_noirq()
903 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
904 readb(priv->base + priv->control_regs[reg]) : in cpg_mssr_suspend_noirq()
905 readl(priv->base + priv->control_regs[reg]); in cpg_mssr_suspend_noirq()
908 /* Save core clocks */ in cpg_mssr_suspend_noirq()
909 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); in cpg_mssr_suspend_noirq()
925 /* Restore core clocks */ in cpg_mssr_resume_noirq()
926 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); in cpg_mssr_resume_noirq()
929 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_resume_noirq()
930 mask = priv->smstpcr_saved[reg].mask; in cpg_mssr_resume_noirq()
934 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
935 oldval = readb(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
937 oldval = readl(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
939 newval |= priv->smstpcr_saved[reg].val & mask; in cpg_mssr_resume_noirq()
943 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq()
944 writeb(newval, priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
946 readb(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
947 barrier_data(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
950 writel(newval, priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
953 mask &= ~priv->smstpcr_saved[reg].val; in cpg_mssr_resume_noirq()
957 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], in cpg_mssr_resume_noirq()
978 kfree(priv->reserved_ids); in cpg_mssr_reserved_exit()
992 * to a non-Linux system will be disabled when Linux is booted. in cpg_mssr_reserved_init()
994 * To avoid such situation, renesas-cpg-mssr assumes the device which has in cpg_mssr_reserved_init()
995 * status = "reserved" is assigned to a non-Linux system, and adds CLK_IGNORE_UNUSED flag in cpg_mssr_reserved_init()
1013 of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) { in cpg_mssr_reserved_init()
1016 if (it.node != priv->np) in cpg_mssr_reserved_init()
1028 return -ENOMEM; in cpg_mssr_reserved_init()
1031 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_reserved_init()
1036 ids[num] = info->num_total_core_clks + idx; in cpg_mssr_reserved_init()
1042 priv->num_reserved_ids = num; in cpg_mssr_reserved_init()
1043 priv->reserved_ids = ids; in cpg_mssr_reserved_init()
1056 if (info->init) { in cpg_mssr_common_init()
1057 error = info->init(dev); in cpg_mssr_common_init()
1062 nclks = info->num_total_core_clks + info->num_hw_mod_clks; in cpg_mssr_common_init()
1065 return -ENOMEM; in cpg_mssr_common_init()
1067 priv->np = np; in cpg_mssr_common_init()
1068 priv->dev = dev; in cpg_mssr_common_init()
1069 spin_lock_init(&priv->rmw_lock); in cpg_mssr_common_init()
1071 priv->base = of_iomap(np, 0); in cpg_mssr_common_init()
1072 if (!priv->base) { in cpg_mssr_common_init()
1073 error = -ENOMEM; in cpg_mssr_common_init()
1077 priv->num_core_clks = info->num_total_core_clks; in cpg_mssr_common_init()
1078 priv->num_mod_clks = info->num_hw_mod_clks; in cpg_mssr_common_init()
1079 priv->last_dt_core_clk = info->last_dt_core_clk; in cpg_mssr_common_init()
1080 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); in cpg_mssr_common_init()
1081 priv->reg_layout = info->reg_layout; in cpg_mssr_common_init()
1082 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { in cpg_mssr_common_init()
1083 priv->status_regs = mstpsr; in cpg_mssr_common_init()
1084 priv->control_regs = smstpcr; in cpg_mssr_common_init()
1085 priv->reset_regs = srcr; in cpg_mssr_common_init()
1086 priv->reset_clear_regs = srstclr; in cpg_mssr_common_init()
1087 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_common_init()
1088 priv->control_regs = stbcr; in cpg_mssr_common_init()
1089 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { in cpg_mssr_common_init()
1090 priv->status_regs = mstpsr_for_gen4; in cpg_mssr_common_init()
1091 priv->control_regs = mstpcr_for_gen4; in cpg_mssr_common_init()
1092 priv->reset_regs = srcr_for_gen4; in cpg_mssr_common_init()
1093 priv->reset_clear_regs = srstclr_for_gen4; in cpg_mssr_common_init()
1095 error = -EINVAL; in cpg_mssr_common_init()
1100 priv->clks[i] = ERR_PTR(-ENOENT); in cpg_mssr_common_init()
1117 if (priv->base) in cpg_mssr_common_init()
1118 iounmap(priv->base); in cpg_mssr_common_init()
1134 for (i = 0; i < info->num_early_core_clks; i++) in cpg_mssr_early_init()
1135 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, in cpg_mssr_early_init()
1138 for (i = 0; i < info->num_early_mod_clks; i++) in cpg_mssr_early_init()
1139 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, in cpg_mssr_early_init()
1146 struct device *dev = &pdev->dev; in cpg_mssr_probe()
1147 struct device_node *np = dev->of_node; in cpg_mssr_probe()
1156 error = cpg_mssr_common_init(dev, dev->of_node, info); in cpg_mssr_probe()
1162 priv->dev = dev; in cpg_mssr_probe()
1165 for (i = 0; i < info->num_core_clks; i++) in cpg_mssr_probe()
1166 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); in cpg_mssr_probe()
1168 for (i = 0; i < info->num_mod_clks; i++) in cpg_mssr_probe()
1169 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); in cpg_mssr_probe()
1177 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, in cpg_mssr_probe()
1178 info->num_core_pm_clks); in cpg_mssr_probe()
1183 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_probe()
1196 .name = "renesas-cpg-mssr",