Lines Matching full:ni

87 	unsigned int ni, nf;  in cpg_pll_8_25_clk_recalc_rate()  local
90 ni = (FIELD_GET(CPG_PLLxCR0_NI8, cr0) + 1) * 2; in cpg_pll_8_25_clk_recalc_rate()
91 rate = parent_rate * ni; in cpg_pll_8_25_clk_recalc_rate()
104 unsigned int min_mult, max_mult, ni, nf; in cpg_pll_8_25_clk_determine_rate() local
115 ni = div64_ul(req->rate, prate); in cpg_pll_8_25_clk_determine_rate()
116 if (ni < min_mult) { in cpg_pll_8_25_clk_determine_rate()
117 ni = min_mult; in cpg_pll_8_25_clk_determine_rate()
120 ni = min(ni, max_mult); in cpg_pll_8_25_clk_determine_rate()
121 nf = div64_ul((u64)(req->rate - prate * ni) << 24, in cpg_pll_8_25_clk_determine_rate()
125 ni = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_8_25_clk_determine_rate()
126 ni = clamp(ni, min_mult, max_mult); in cpg_pll_8_25_clk_determine_rate()
129 req->rate = prate * ni + mul_u64_u32_shr(req->best_parent_rate, nf, 24); in cpg_pll_8_25_clk_determine_rate()
140 unsigned int ni, nf; in cpg_pll_8_25_clk_set_rate() local
144 ni = div64_ul(rate, prate); in cpg_pll_8_25_clk_set_rate()
145 if (ni < 1) { in cpg_pll_8_25_clk_set_rate()
146 ni = 1; in cpg_pll_8_25_clk_set_rate()
149 ni = min(ni, 256U); in cpg_pll_8_25_clk_set_rate()
150 nf = div64_ul((u64)(rate - prate * ni) << 24, in cpg_pll_8_25_clk_set_rate()
154 ni = DIV_ROUND_CLOSEST_ULL(rate, prate); in cpg_pll_8_25_clk_set_rate()
155 ni = clamp(ni, 1U, 256U); in cpg_pll_8_25_clk_set_rate()
162 FIELD_PREP(CPG_PLLxCR0_NI8, ni - 1)); in cpg_pll_8_25_clk_set_rate()
201 unsigned int ni, nf; in cpg_pll_9_24_clk_recalc_rate() local
204 ni = FIELD_GET(CPG_PLLxCR0_NI9, cr0) + 1; in cpg_pll_9_24_clk_recalc_rate()
205 rate = parent_rate * ni; in cpg_pll_9_24_clk_recalc_rate()