Lines Matching full:nf
87 unsigned int ni, nf; in cpg_pll_8_25_clk_recalc_rate() local
93 nf = FIELD_GET(CPG_PLLxCR1_NF25, readl(pll_clk->pllcr1_reg)); in cpg_pll_8_25_clk_recalc_rate()
94 rate += mul_u64_u32_shr(parent_rate, nf, 24); in cpg_pll_8_25_clk_recalc_rate()
104 unsigned int min_mult, max_mult, ni, nf; in cpg_pll_8_25_clk_determine_rate() local
118 nf = 0; in cpg_pll_8_25_clk_determine_rate()
121 nf = div64_ul((u64)(req->rate - prate * ni) << 24, in cpg_pll_8_25_clk_determine_rate()
127 nf = 0; in cpg_pll_8_25_clk_determine_rate()
129 req->rate = prate * ni + mul_u64_u32_shr(req->best_parent_rate, nf, 24); in cpg_pll_8_25_clk_determine_rate()
140 unsigned int ni, nf; in cpg_pll_8_25_clk_set_rate() local
147 nf = 0; in cpg_pll_8_25_clk_set_rate()
150 nf = div64_ul((u64)(rate - prate * ni) << 24, in cpg_pll_8_25_clk_set_rate()
165 FIELD_PREP(CPG_PLLxCR1_NF25, nf)); in cpg_pll_8_25_clk_set_rate()
201 unsigned int ni, nf; in cpg_pll_9_24_clk_recalc_rate() local
207 nf = FIELD_GET(CPG_PLLxCR1_NF24, readl(pll_clk->pllcr1_reg)); in cpg_pll_9_24_clk_recalc_rate()
208 rate += mul_u64_u32_shr(parent_rate, nf, 24); in cpg_pll_9_24_clk_recalc_rate()