56 #define CPG_PLLxCR0_NI8		GENMASK(27, 20)	/* Integer mult. factor */
57 #define CPG_PLLxCR1_NF25	GENMASK(24, 0)	/* Fractional mult. factor */
60 #define CPG_PLLxCR0_NI9		GENMASK(28, 20)	/* Integer mult. factor */
61 #define CPG_PLLxCR1_NF24	GENMASK(23, 0)	/* Fractional mult. factor */
282 	unsigned int mult;  in cpg_z_clk_recalc_rate()  local
286 	mult = 32 - (val >> __ffs(zclk->mask));  in cpg_z_clk_recalc_rate()
288 	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,  in cpg_z_clk_recalc_rate()
296 	unsigned int min_mult, max_mult, mult;  in cpg_z_clk_determine_rate()  local
316 	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);  in cpg_z_clk_determine_rate()
317 	mult = clamp(mult, min_mult, max_mult);  in cpg_z_clk_determine_rate()
319 	req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);  in cpg_z_clk_determine_rate()
327 	unsigned int mult;  in cpg_z_clk_set_rate()  local
330 	mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,  in cpg_z_clk_set_rate()
332 	mult = clamp(mult, 1U, 32U);  in cpg_z_clk_set_rate()
337 	cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));  in cpg_z_clk_set_rate()
425 	unsigned int mult = 1;  in rcar_gen4_cpg_clk_register()  local
439 		mult = cpg_pll_config->pll1_mult;  in rcar_gen4_cpg_clk_register()
444 		mult = cpg_pll_config->pll5_mult;  in rcar_gen4_cpg_clk_register()
450 		mult = (FIELD_GET(CPG_PLLxCR_STC, value) + 1) * 2;  in rcar_gen4_cpg_clk_register()
501 		mult = 1;  in rcar_gen4_cpg_clk_register()
531 					 __clk_get_name(parent), 0, mult, div);  in rcar_gen4_cpg_clk_register()