37 #define CPG_PLLnCR_STC_MASK	GENMASK(30, 24)	/* PLL Circuit Mult. Ratio */
56 	unsigned int mult;  in cpg_pll_clk_recalc_rate()  local
60 	mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1;  in cpg_pll_clk_recalc_rate()
62 	return parent_rate * mult * pll_clk->fixed_mult;  in cpg_pll_clk_recalc_rate()
69 	unsigned int min_mult, max_mult, mult;  in cpg_pll_clk_determine_rate()  local
78 	mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);  in cpg_pll_clk_determine_rate()
79 	mult = clamp(mult, min_mult, max_mult);  in cpg_pll_clk_determine_rate()
81 	req->rate = prate * mult;  in cpg_pll_clk_determine_rate()
89 	unsigned int mult, i;  in cpg_pll_clk_set_rate()  local
92 	mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);  in cpg_pll_clk_set_rate()
93 	mult = clamp(mult, 1U, 128U);  in cpg_pll_clk_set_rate()
97 	val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);  in cpg_pll_clk_set_rate()
119 						unsigned int mult,  in cpg_pll_clk_register()  argument
140 	pll_clk->fixed_mult = mult;	/* PLL refclk x (setting + 1) x mult */  in cpg_pll_clk_register()
157  *        clk->rate = (parent->rate * mult / 32 ) / fixed_div
179 	unsigned int mult;  in cpg_z_clk_recalc_rate()  local
183 	mult = 32 - (val >> __ffs(zclk->mask));  in cpg_z_clk_recalc_rate()
185 	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,  in cpg_z_clk_recalc_rate()
193 	unsigned int min_mult, max_mult, mult;  in cpg_z_clk_determine_rate()  local
213 	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);  in cpg_z_clk_determine_rate()
214 	mult = clamp(mult, min_mult, max_mult);  in cpg_z_clk_determine_rate()
216 	req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);  in cpg_z_clk_determine_rate()
224 	unsigned int mult;  in cpg_z_clk_set_rate()  local
227 	mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,  in cpg_z_clk_set_rate()
229 	mult = clamp(mult, 1U, 32U);  in cpg_z_clk_set_rate()
234 	cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));  in cpg_z_clk_set_rate()
353 	unsigned int mult = 1;  in rcar_gen3_cpg_clk_register()  local
376 		mult = cpg_pll_config->pll1_mult;  in rcar_gen3_cpg_clk_register()
390 		mult = cpg_pll_config->pll3_mult;  in rcar_gen3_cpg_clk_register()
402 		mult = (((value >> 24) & 0x7f) + 1) * 2;  in rcar_gen3_cpg_clk_register()
457 		mult = 1;  in rcar_gen3_cpg_clk_register()
538 					 __clk_get_name(parent), 0, mult, div);  in rcar_gen3_cpg_clk_register()