Lines Matching full:4
46 {1, 4},
49 {4, 64},
73 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
81 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
82 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
83 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
84 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),
85 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),
86 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),
87 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),
88 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),
89 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),
90 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),
91 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),
92 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),
93 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),
97 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
98 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),
99 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),
100 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),
101 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),
102 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),
103 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),
104 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),
105 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),
106 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),
108 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),
128 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
129 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
134 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
135 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
136 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
137 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
138 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
139 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
140 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
141 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
142 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
143 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
144 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
145 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
146 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */