clk/renesas/r9a09g057-cpg.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
46 	{1, 4},
66 	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
68 	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
69 	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
70 	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
73 	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
76 	DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
77 	DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
87 	DEF_MOD("gtm_6_pclk",			CLK_PLLCLN_DIV16, 4, 9, 2, 9),
95 	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17),
98 	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19),
99 	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20),
100 	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21),
101 	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22),
102 	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23),
103 	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24),
104 	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25),
105 	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26),
106 	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27),
113 	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9),
125 	DEF_RST(7, 0, 3, 1),		/* GTM_3_PRESETZ */
126 	DEF_RST(7, 1, 3, 2),		/* GTM_4_PRESETZ */
133 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
134 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
135 	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
136 	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
137 	DEF_RST(9, 10, 4, 11),		/* RIIC_2_MRST */
138 	DEF_RST(9, 11, 4, 12),		/* RIIC_3_MRST */
139 	DEF_RST(9, 12, 4, 13),		/* RIIC_4_MRST */
140 	DEF_RST(9, 13, 4, 14),		/* RIIC_5_MRST */
141 	DEF_RST(9, 14, 4, 15),		/* RIIC_6_MRST */
142 	DEF_RST(9, 15, 4, 16),		/* RIIC_7_MRST */
146 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */