Lines Matching refs:DEF_REG_CONF
268 DEF_REG_CONF(0, 0),
271 DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
274 DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
277 DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
280 DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
283 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
286 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
289 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
292 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)),
295 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)),
298 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)),
301 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
304 DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
307 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),
310 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),
313 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),
316 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),
319 DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
322 DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),