1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2014  Ulrich Hecht
8 #include <linux/clk-provider.h>
23 #define CPG_FRQCRA	0x00
24 #define CPG_FRQCRB	0x04
25 #define CPG_SD0CKCR	0x74
26 #define CPG_SD1CKCR	0x78
27 #define CPG_SD2CKCR	0x7c
28 #define CPG_PLLECR	0xd0
29 #define CPG_PLL0CR	0xd8
30 #define CPG_PLL1CR	0x28
31 #define CPG_PLL2CR	0x2c
32 #define CPG_PLL3CR	0xdc
33 #define CPG_CKSCR	0xc0
34 #define CPG_DSI0PHYCR	0x6c
35 #define CPG_DSI1PHYCR	0x70
38 	const char *name;  member
73 			  void __iomem *base, const char *name)  in sh73a0_cpg_register_clock()  argument
81 	if (!strcmp(name, "main")) {  in sh73a0_cpg_register_clock()
87 	} else if (!strncmp(name, "pll", 3)) {  in sh73a0_cpg_register_clock()
89 		u32 enable_bit = name[3] - '0';  in sh73a0_cpg_register_clock()
106 			return ERR_PTR(-EINVAL);  in sh73a0_cpg_register_clock()
115 	} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {  in sh73a0_cpg_register_clock()
116 		u32 phy_no = name[3] - '0';  in sh73a0_cpg_register_clock()
126 	} else if (!strcmp(name, "z")) {  in sh73a0_cpg_register_clock()
133 		const struct div4_clk *c;  in sh73a0_cpg_register_clock()  local
135 		for (c = div4_clks; c->name; c++) {  in sh73a0_cpg_register_clock()
136 			if (!strcmp(name, c->name)) {  in sh73a0_cpg_register_clock()
137 				parent_name = c->parent;  in sh73a0_cpg_register_clock()
139 				reg = c->reg;  in sh73a0_cpg_register_clock()
140 				shift = c->shift;  in sh73a0_cpg_register_clock()
145 		if (!c->name)  in sh73a0_cpg_register_clock()
146 			return ERR_PTR(-EINVAL);  in sh73a0_cpg_register_clock()
150 		return clk_register_fixed_factor(NULL, name, parent_name, 0,  in sh73a0_cpg_register_clock()
153 		return clk_register_divider_table(NULL, name, parent_name, 0,  in sh73a0_cpg_register_clock()
155 						  table, &cpg->lock);  in sh73a0_cpg_register_clock()
167 	num_clks = of_property_count_strings(np, "clock-output-names");  in sh73a0_cpg_clocks_init()
182 	spin_lock_init(&cpg->lock);  in sh73a0_cpg_clocks_init()
184 	cpg->data.clks = clks;  in sh73a0_cpg_clocks_init()
185 	cpg->data.clk_num = num_clks;  in sh73a0_cpg_clocks_init()
197 		const char *name;  in sh73a0_cpg_clocks_init()  local
200 		of_property_read_string_index(np, "clock-output-names", i,  in sh73a0_cpg_clocks_init()
201 					      &name);  in sh73a0_cpg_clocks_init()
203 		clk = sh73a0_cpg_register_clock(np, cpg, base, name);  in sh73a0_cpg_clocks_init()
206 			       __func__, np, name, PTR_ERR(clk));  in sh73a0_cpg_clocks_init()
208 			cpg->data.clks[i] = clk;  in sh73a0_cpg_clocks_init()
211 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);  in sh73a0_cpg_clocks_init()
213 CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",