Lines Matching refs:CLK_BASE
665 #define CLK_BASE(_name, _parent, _recalc) { \ macro
680 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
684 { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
688 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
689 { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
693 { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
694 { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
698 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
699 { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
700 { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
704 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
705 { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
706 { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
707 { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
708 { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
712 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
713 { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }