Lines Matching +full:pll +full:- +full:periph
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include <linux/reset-controller.h>
191 { CLK_PERIPH("10000500.uart", "periph") },
192 { CLK_PERIPH("10000900.i2c", "periph") },
193 { CLK_PERIPH("10000a00.i2s", "periph") },
196 { CLK_PERIPH("10000c00.uartlite", "periph") },
202 { CLK_PERIPH("10000100.timer", "periph") },
203 { CLK_PERIPH("10000120.watchdog", "periph") },
204 { CLK_PERIPH("10000500.uart", "periph") },
205 { CLK_PERIPH("10000900.i2c", "periph") },
206 { CLK_PERIPH("10000a00.i2s", "periph") },
209 { CLK_PERIPH("10000c00.uartlite", "periph") },
214 { CLK_PERIPH("10000100.timer", "periph") },
215 { CLK_PERIPH("10000120.watchdog", "periph") },
216 { CLK_PERIPH("10000900.i2c", "periph") },
220 { CLK_PERIPH("10000c00.uart0", "periph") },
221 { CLK_PERIPH("10000d00.uart1", "periph") },
222 { CLK_PERIPH("10000e00.uart2", "periph") },
230 struct clk_hw **hws = clk_data->hws; in mtmips_register_pherip_clocks()
232 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed + in mtmips_register_pherip_clocks()
233 priv->data->num_clk_factor; in mtmips_register_pherip_clocks()
236 for (i = 0; i < priv->data->num_clk_periph; i++) { in mtmips_register_pherip_clocks()
239 sclk = &priv->data->clk_periph[i]; in mtmips_register_pherip_clocks()
240 ret = of_clk_hw_register(np, &sclk->hw); in mtmips_register_pherip_clocks()
246 hws[idx] = &sclk->hw; in mtmips_register_pherip_clocks()
252 while (--i >= 0) { in mtmips_register_pherip_clocks()
253 sclk = &priv->data->clk_periph[i]; in mtmips_register_pherip_clocks()
254 clk_hw_unregister(&sclk->hw); in mtmips_register_pherip_clocks()
271 CLK_FIXED("periph", "xtal", 40000000)
276 CLK_FIXED("periph", "xtal", 40000000)
282 struct clk_hw **hws = clk_data->hws; in mtmips_register_fixed_clocks()
284 size_t idx_start = priv->data->num_clk_base; in mtmips_register_fixed_clocks()
287 for (i = 0; i < priv->data->num_clk_fixed; i++) { in mtmips_register_fixed_clocks()
290 sclk = &priv->data->clk_fixed[i]; in mtmips_register_fixed_clocks()
291 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name, in mtmips_register_fixed_clocks()
292 sclk->parent, 0, in mtmips_register_fixed_clocks()
293 sclk->rate); in mtmips_register_fixed_clocks()
294 if (IS_ERR(sclk->hw)) { in mtmips_register_fixed_clocks()
295 ret = PTR_ERR(sclk->hw); in mtmips_register_fixed_clocks()
300 hws[idx] = sclk->hw; in mtmips_register_fixed_clocks()
306 while (--i >= 0) { in mtmips_register_fixed_clocks()
307 sclk = &priv->data->clk_fixed[i]; in mtmips_register_fixed_clocks()
308 clk_hw_unregister_fixed_rate(sclk->hw); in mtmips_register_fixed_clocks()
333 struct clk_hw **hws = clk_data->hws; in mtmips_register_factor_clocks()
335 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed; in mtmips_register_factor_clocks()
338 for (i = 0; i < priv->data->num_clk_factor; i++) { in mtmips_register_factor_clocks()
341 sclk = &priv->data->clk_factor[i]; in mtmips_register_factor_clocks()
342 sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name, in mtmips_register_factor_clocks()
343 sclk->parent, sclk->flags, in mtmips_register_factor_clocks()
344 sclk->mult, sclk->div); in mtmips_register_factor_clocks()
345 if (IS_ERR(sclk->hw)) { in mtmips_register_factor_clocks()
346 ret = PTR_ERR(sclk->hw); in mtmips_register_factor_clocks()
351 hws[idx] = sclk->hw; in mtmips_register_factor_clocks()
357 while (--i >= 0) { in mtmips_register_factor_clocks()
358 sclk = &priv->data->clk_factor[i]; in mtmips_register_factor_clocks()
359 clk_hw_unregister_fixed_factor(sclk->hw); in mtmips_register_factor_clocks()
373 struct regmap *sysc = clk->priv->sysc; in rt5350_xtal_recalc_rate()
387 struct regmap *sysc = clk->priv->sysc; in rt5350_cpu_recalc_rate()
418 struct regmap *sysc = clk->priv->sysc; in rt3352_cpu_recalc_rate()
438 struct regmap *sysc = clk->priv->sysc; in rt305x_cpu_recalc_rate()
458 struct regmap *sysc = clk->priv->sysc; in rt3883_cpu_recalc_rate()
482 struct regmap *sysc = clk->priv->sysc; in rt3883_bus_recalc_rate()
508 struct regmap *sysc = clk->priv->sysc; in rt2880_cpu_recalc_rate()
544 struct regmap *sysc = clk->priv->sysc; in mt7620_pll_recalc_rate()
584 struct regmap *sysc = clk->priv->sysc; in mt7620_cpu_recalc_rate()
608 struct regmap *sysc = clk->priv->sysc; in mt7620_bus_recalc_rate()
632 struct regmap *sysc = clk->priv->sysc; in mt7620_periph_recalc_rate()
646 struct regmap *sysc = clk->priv->sysc; in mt76x8_xtal_recalc_rate()
705 { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
706 { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
707 { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
720 struct clk_hw **hws = clk_data->hws; in mtmips_register_clocks()
724 for (i = 0; i < priv->data->num_clk_base; i++) { in mtmips_register_clocks()
725 sclk = &priv->data->clk_base[i]; in mtmips_register_clocks()
726 sclk->priv = priv; in mtmips_register_clocks()
727 ret = of_clk_hw_register(np, &sclk->hw); in mtmips_register_clocks()
733 hws[i] = &sclk->hw; in mtmips_register_clocks()
739 while (--i >= 0) { in mtmips_register_clocks()
740 sclk = &priv->data->clk_base[i]; in mtmips_register_clocks()
741 clk_hw_unregister(&sclk->hw); in mtmips_register_clocks()
825 .compatible = "ralink,rt2880-reset",
829 .compatible = "ralink,rt2880-sysc",
833 .compatible = "ralink,rt3050-sysc",
837 .compatible = "ralink,rt3052-sysc",
841 .compatible = "ralink,rt3352-sysc",
845 .compatible = "ralink,rt3883-sysc",
849 .compatible = "ralink,rt5350-sysc",
853 .compatible = "ralink,mt7620-sysc",
857 .compatible = "ralink,mt7628-sysc",
861 .compatible = "ralink,mt7688-sysc",
872 if (!of_device_is_compatible(node, "ralink,mt7620-sysc")) in mtmips_clk_regs_init()
880 regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); in mtmips_clk_regs_init()
883 regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t); in mtmips_clk_regs_init()
898 priv->sysc = syscon_node_to_regmap(node); in mtmips_clk_init()
899 if (IS_ERR(priv->sysc)) { in mtmips_clk_init()
910 data = match->data; in mtmips_clk_init()
911 priv->data = data; in mtmips_clk_init()
912 count = priv->data->num_clk_base + priv->data->num_clk_fixed + in mtmips_clk_init()
913 priv->data->num_clk_factor + priv->data->num_clk_periph; in mtmips_clk_init()
942 clk_data->num = count; in mtmips_clk_init()
953 for (i = 0; i < priv->data->num_clk_periph; i++) { in mtmips_clk_init()
954 struct mtmips_clk *sclk = &priv->data->clk_periph[i]; in mtmips_clk_init()
956 clk_hw_unregister(&sclk->hw); in mtmips_clk_init()
960 for (i = 0; i < priv->data->num_clk_factor; i++) { in mtmips_clk_init()
961 struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i]; in mtmips_clk_init()
963 clk_hw_unregister_fixed_factor(sclk->hw); in mtmips_clk_init()
967 for (i = 0; i < priv->data->num_clk_fixed; i++) { in mtmips_clk_init()
968 struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i]; in mtmips_clk_init()
970 clk_hw_unregister_fixed_rate(sclk->hw); in mtmips_clk_init()
974 for (i = 0; i < priv->data->num_clk_base; i++) { in mtmips_clk_init()
975 struct mtmips_clk *sclk = &priv->data->clk_base[i]; in mtmips_clk_init()
977 clk_hw_unregister(&sclk->hw); in mtmips_clk_init()
986 CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
987 CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
988 CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
989 CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
990 CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
991 CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
992 CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
993 CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
994 CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
1010 struct regmap *sysc = data->sysc; in mtmips_assert_device()
1019 struct regmap *sysc = data->sysc; in mtmips_deassert_device()
1039 unsigned long id = reset_spec->args[0]; in mtmips_rst_xlate()
1041 if (id == 0 || id >= rcdev->nr_resets) in mtmips_rst_xlate()
1042 return -EINVAL; in mtmips_rst_xlate()
1059 return -ENOMEM; in mtmips_reset_init()
1061 rst_data->sysc = sysc; in mtmips_reset_init()
1062 rst_data->rcdev.ops = &reset_ops; in mtmips_reset_init()
1063 rst_data->rcdev.owner = THIS_MODULE; in mtmips_reset_init()
1064 rst_data->rcdev.nr_resets = 32; in mtmips_reset_init()
1065 rst_data->rcdev.of_reset_n_cells = 1; in mtmips_reset_init()
1066 rst_data->rcdev.of_xlate = mtmips_rst_xlate; in mtmips_reset_init()
1067 rst_data->rcdev.of_node = dev_of_node(dev); in mtmips_reset_init()
1069 return devm_reset_controller_register(dev, &rst_data->rcdev); in mtmips_reset_init()
1074 struct device_node *np = pdev->dev.of_node; in mtmips_clk_probe()
1075 struct device *dev = &pdev->dev; in mtmips_clk_probe()
1081 return -ENOMEM; in mtmips_clk_probe()
1083 priv->sysc = syscon_node_to_regmap(np); in mtmips_clk_probe()
1084 if (IS_ERR(priv->sysc)) in mtmips_clk_probe()
1085 return dev_err_probe(dev, PTR_ERR(priv->sysc), in mtmips_clk_probe()
1088 ret = mtmips_reset_init(dev, priv->sysc); in mtmips_clk_probe()
1098 .name = "mtmips-clk",