clk/qcom/videocc-sm8250.c

30 	{ 249600000, 2000000000, 0 },
34 	.l = 0x25,
35 	.alpha = 0x8000,
36 	.config_ctl_val = 0x20485699,
37 	.config_ctl_hi_val = 0x00002261,
38 	.config_ctl_hi1_val = 0x329A699C,
39 	.user_ctl_val = 0x00000000,
40 	.user_ctl_hi_val = 0x00000805,
41 	.user_ctl_hi1_val = 0x00000000,
45 	.offset = 0x42c,
62 	.l = 0x2B,
63 	.alpha = 0xC000,
64 	.config_ctl_val = 0x20485699,
65 	.config_ctl_hi_val = 0x00002261,
66 	.config_ctl_hi1_val = 0x329A699C,
67 	.user_ctl_val = 0x00000000,
68 	.user_ctl_hi_val = 0x00000805,
69 	.user_ctl_hi1_val = 0x00000000,
73 	.offset = 0x7d0,
90 	{ P_BI_TCXO, 0 },
100 	{ P_BI_TCXO, 0 },
110 	F(19200000, P_BI_TCXO, 1, 0, 0),
111 	F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
112 	F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
113 	F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
114 	F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
119 	.cmd_rcgr = 0xb94,
120 	.mnd_width = 0,
134 	F(19200000, P_BI_TCXO, 1, 0, 0),
135 	F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
136 	F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
137 	F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
142 	.cmd_rcgr = 0xbb4,
143 	.mnd_width = 0,
157 	.reg = 0xc54,
158 	.shift = 0,
172 	.reg = 0xd54,
173 	.shift = 0,
187 	.reg = 0xcf4,
188 	.shift = 0,
202 	.halt_reg = 0xc34,
205 		.enable_reg = 0xc34,
206 		.enable_mask = BIT(0),
220 	.halt_reg = 0xd34,
223 		.enable_reg = 0xd34,
224 		.enable_mask = BIT(0),
238 	.halt_reg = 0xdf4,
241 		.enable_reg = 0xdf4,
242 		.enable_mask = BIT(0),
256 	.halt_reg = 0xcd4,
259 		.enable_reg = 0xcd4,
260 		.enable_mask = BIT(0),
274 	.gdscr = 0xbf8,
278 	.flags = 0,
283 	.gdscr = 0xc98,
287 	.flags = 0,
292 	.gdscr = 0xd18,
301 	.gdscr = 0xd98,
324 	[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
325 	[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
326 	[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, .bit = 2, .udelay = 150 },
327 	[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
328 	[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
329 	[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, .bit = 2, .udelay = 150 },
330 	[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
344 	.max_register = 0xf4c,
387 	qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */  in video_cc_sm8250_probe()
388 	qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */  in video_cc_sm8250_probe()