clk/qcom/nsscc-qca8k.c

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/qcom,qca8k-nsscc.h>
17 #include <dt-bindings/reset/qcom,qca8k-nsscc.h>
19 #include "clk-branch.h"
20 #include "clk-rcg.h"
21 #include "clk-regmap.h"
22 #include "clk-regmap-divider.h"
23 #include "clk-regmap-mux.h"
2020  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2022  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2045 		dev_err_ratelimited(&bus->dev, "fail to read qca8k mii register\n");  in qca8k_mii_read()
2060 		dev_err_ratelimited(&bus->dev, "fail to write qca8k mii register\n");  in qca8k_mii_write()
2069 		dev_err_ratelimited(&bus->dev, "fail to set page\n");  in qca8k_mii_page_set()
2083 	mutex_lock(&bus->mdio_lock);  in qca8k_regmap_read()
2091 	mutex_unlock(&bus->mdio_lock);  in qca8k_regmap_read()
2104 	mutex_lock(&bus->mdio_lock);  in qca8k_regmap_write()
2112 	mutex_unlock(&bus->mdio_lock);  in qca8k_regmap_write()
2127 	mutex_lock(&bus->mdio_lock);  in qca8k_regmap_update_bits()
2141 	mutex_unlock(&bus->mdio_lock);  in qca8k_regmap_update_bits()
2165  * The reference clock of QCA8k NSSCC needs to be enabled to make sure
2193 	ret = nss_cc_qca8k_clock_enable_and_reset(&mdiodev->dev);  in nss_cc_qca8k_probe()
2195 		return dev_err_probe(&mdiodev->dev, ret, "Fail to reset NSSCC\n");  in nss_cc_qca8k_probe()
2197 	regmap = devm_regmap_init(&mdiodev->dev, NULL, mdiodev->bus, nss_cc_qca8k_desc.config);  in nss_cc_qca8k_probe()
2199 		return dev_err_probe(&mdiodev->dev, PTR_ERR(regmap), "Failed to init regmap\n");  in nss_cc_qca8k_probe()
2201 	return qcom_cc_really_probe(&mdiodev->dev, &nss_cc_qca8k_desc, regmap);  in nss_cc_qca8k_probe()
2205 	{ .compatible = "qcom,qca8084-nsscc" },
2212 		.name = "qcom,qca8k-nsscc",
2220 MODULE_DESCRIPTION("QCOM NSS_CC QCA8K Driver");