Lines Matching +full:0 +full:x3150
64 { 1500000000, 2000000000, 0 },
70 { 1500000000, 2000000000, 0 },
74 { 500000000, 1500000000, 0 },
78 .offset = 0x0,
83 .enable_reg = 0x100,
84 .enable_mask = BIT(0),
97 .offset = 0x0,
112 .offset = 0x30,
117 .enable_reg = 0x100,
131 .offset = 0x30,
146 .offset = 0x4100,
161 .offset = 0x4100,
176 .offset = 0x60,
191 .offset = 0x60,
206 .offset = 0x90,
221 .offset = 0x90,
236 .offset = 0xc0,
251 .offset = 0xc0,
266 .offset = 0x4130,
281 .offset = 0x4130,
296 .offset = 0x4200,
311 .offset = 0x4200,
326 { P_XO, 0 },
336 { P_XO, 0 },
348 { P_XO, 0 },
360 { P_XO, 0 },
372 { P_XO, 0 },
386 { P_XO, 0 },
402 { P_XO, 0 },
418 { P_XO, 0 },
434 { P_XO, 0 },
450 { P_XO, 0 },
468 { P_XO, 0 },
488 { P_XO, 0 },
508 F(19200000, P_XO, 1, 0, 0),
509 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
510 F(80000000, P_MMPLL0, 10, 0, 0),
515 .cmd_rcgr = 0x5000,
528 F(19200000, P_XO, 1, 0, 0),
529 F(75000000, P_GPLL0_DIV, 4, 0, 0),
530 F(100000000, P_GPLL0, 6, 0, 0),
531 F(171430000, P_GPLL0, 3.5, 0, 0),
532 F(200000000, P_GPLL0, 3, 0, 0),
533 F(320000000, P_MMPLL0, 2.5, 0, 0),
534 F(400000000, P_MMPLL0, 2, 0, 0),
539 .cmd_rcgr = 0x5040,
552 .cmd_rcgr = 0x5090,
566 .cmd_rcgr = 0x4000,
585 F(19200000, P_XO, 1, 0, 0),
590 .cmd_rcgr = 0x4090,
603 .cmd_rcgr = 0x4010,
615 F(19200000, P_XO, 1, 0, 0),
616 F(50000000, P_GPLL0, 12, 0, 0),
621 .cmd_rcgr = 0x4060,
634 F(75000000, P_GPLL0_DIV, 4, 0, 0),
635 F(150000000, P_GPLL0, 4, 0, 0),
636 F(346666667, P_MMPLL3, 3, 0, 0),
637 F(520000000, P_MMPLL3, 2, 0, 0),
642 .cmd_rcgr = 0x1000,
656 .cmd_rcgr = 0x1060,
670 .cmd_rcgr = 0x1080,
684 .cmd_rcgr = 0x2000,
698 .cmd_rcgr = 0x2020,
712 F(85714286, P_GPLL0, 7, 0, 0),
713 F(100000000, P_GPLL0, 6, 0, 0),
714 F(150000000, P_GPLL0, 4, 0, 0),
715 F(171428571, P_GPLL0, 3.5, 0, 0),
716 F(200000000, P_GPLL0, 3, 0, 0),
717 F(275000000, P_MMPLL5, 3, 0, 0),
718 F(300000000, P_GPLL0, 2, 0, 0),
719 F(330000000, P_MMPLL5, 2.5, 0, 0),
720 F(412500000, P_MMPLL5, 2, 0, 0),
725 .cmd_rcgr = 0x2040,
743 .cmd_rcgr = 0x2060,
757 F(19200000, P_XO, 1, 0, 0),
762 .cmd_rcgr = 0x2080,
775 F(19200000, P_XO, 1, 0, 0),
780 .cmd_rcgr = 0x2100,
793 .cmd_rcgr = 0x2120,
806 .cmd_rcgr = 0x2140,
819 F(19200000, P_XO, 1, 0, 0),
824 .cmd_rcgr = 0x2160,
837 .cmd_rcgr = 0x2180,
860 .cmd_rcgr = 0x3420,
874 .cmd_rcgr = 0x3450,
888 F(4800000, P_XO, 4, 0, 0),
891 F(9600000, P_XO, 2, 0, 0),
893 F(19200000, P_XO, 1, 0, 0),
902 .cmd_rcgr = 0x3360,
916 .cmd_rcgr = 0x3390,
930 .cmd_rcgr = 0x33c0,
944 .cmd_rcgr = 0x33f0,
958 F(19200000, P_XO, 1, 0, 0),
959 F(37500000, P_GPLL0, 16, 0, 0),
960 F(50000000, P_GPLL0, 12, 0, 0),
961 F(100000000, P_GPLL0, 6, 0, 0),
966 .cmd_rcgr = 0x3300,
980 F(100000000, P_GPLL0_DIV, 3, 0, 0),
981 F(200000000, P_GPLL0, 3, 0, 0),
982 F(266666667, P_MMPLL0, 3, 0, 0),
987 .cmd_rcgr = 0x3000,
1000 .cmd_rcgr = 0x3030,
1013 .cmd_rcgr = 0x3060,
1026 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1027 F(200000000, P_GPLL0, 3, 0, 0),
1028 F(320000000, P_MMPLL4, 3, 0, 0),
1029 F(384000000, P_MMPLL4, 2.5, 0, 0),
1034 .cmd_rcgr = 0x3240,
1047 .cmd_rcgr = 0x3260,
1060 .cmd_rcgr = 0x3280,
1073 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1074 F(150000000, P_GPLL0, 4, 0, 0),
1075 F(228571429, P_MMPLL0, 3.5, 0, 0),
1076 F(266666667, P_MMPLL0, 3, 0, 0),
1077 F(320000000, P_MMPLL0, 2.5, 0, 0),
1078 F(480000000, P_MMPLL4, 2, 0, 0),
1083 .cmd_rcgr = 0x3500,
1096 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1097 F(150000000, P_GPLL0, 4, 0, 0),
1098 F(228571429, P_MMPLL0, 3.5, 0, 0),
1099 F(266666667, P_MMPLL0, 3, 0, 0),
1100 F(320000000, P_MMPLL0, 2.5, 0, 0),
1105 .cmd_rcgr = 0x3540,
1118 .cmd_rcgr = 0x3560,
1131 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1132 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1133 F(300000000, P_GPLL0, 2, 0, 0),
1134 F(320000000, P_MMPLL0, 2.5, 0, 0),
1135 F(480000000, P_MMPLL4, 2, 0, 0),
1136 F(600000000, P_GPLL0, 1, 0, 0),
1141 .cmd_rcgr = 0x3600,
1154 .cmd_rcgr = 0x3620,
1167 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1168 F(200000000, P_GPLL0, 3, 0, 0),
1169 F(320000000, P_MMPLL0, 2.5, 0, 0),
1170 F(480000000, P_MMPLL4, 2, 0, 0),
1171 F(640000000, P_MMPLL4, 1.5, 0, 0),
1176 .cmd_rcgr = 0x3640,
1189 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1190 F(200000000, P_GPLL0, 3, 0, 0),
1191 F(266666667, P_MMPLL0, 3, 0, 0),
1192 F(480000000, P_MMPLL4, 2, 0, 0),
1193 F(600000000, P_GPLL0, 1, 0, 0),
1198 .cmd_rcgr = 0x3090,
1211 .cmd_rcgr = 0x3100,
1224 .cmd_rcgr = 0x3160,
1237 .cmd_rcgr = 0x31c0,
1250 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1251 F(200000000, P_GPLL0, 3, 0, 0),
1252 F(400000000, P_MMPLL0, 2, 0, 0),
1257 .cmd_rcgr = 0x3b00,
1270 .halt_reg = 0x5024,
1272 .enable_reg = 0x5024,
1273 .enable_mask = BIT(0),
1287 .halt_reg = 0x5054,
1289 .enable_reg = 0x5054,
1290 .enable_mask = BIT(0),
1304 .halt_reg = 0x5018,
1306 .enable_reg = 0x5018,
1307 .enable_mask = BIT(0),
1321 .halt_reg = 0x5014,
1323 .enable_reg = 0x5014,
1324 .enable_mask = BIT(0),
1337 .halt_reg = 0x5074,
1339 .enable_reg = 0x5074,
1340 .enable_mask = BIT(0),
1354 .halt_reg = 0x3c44,
1356 .enable_reg = 0x3c44,
1357 .enable_mask = BIT(0),
1371 .halt_reg = 0x3c48,
1373 .enable_reg = 0x3c48,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0x3c04,
1390 .enable_reg = 0x3c04,
1391 .enable_mask = BIT(0),
1405 .halt_reg = 0x3c08,
1407 .enable_reg = 0x3c08,
1408 .enable_mask = BIT(0),
1422 .halt_reg = 0x3c14,
1424 .enable_reg = 0x3c14,
1425 .enable_mask = BIT(0),
1439 .halt_reg = 0x3c18,
1441 .enable_reg = 0x3c18,
1442 .enable_mask = BIT(0),
1456 .halt_reg = 0x3c24,
1458 .enable_reg = 0x3c24,
1459 .enable_mask = BIT(0),
1473 .halt_reg = 0x3c28,
1475 .enable_reg = 0x3c28,
1476 .enable_mask = BIT(0),
1490 .halt_reg = 0x2474,
1492 .enable_reg = 0x2474,
1493 .enable_mask = BIT(0),
1507 .halt_reg = 0x2478,
1509 .enable_reg = 0x2478,
1510 .enable_mask = BIT(0),
1524 .halt_reg = 0x2444,
1526 .enable_reg = 0x2444,
1527 .enable_mask = BIT(0),
1541 .halt_reg = 0x2448,
1543 .enable_reg = 0x2448,
1544 .enable_mask = BIT(0),
1558 .halt_reg = 0x2454,
1560 .enable_reg = 0x2454,
1561 .enable_mask = BIT(0),
1575 .halt_reg = 0x2458,
1577 .enable_reg = 0x2458,
1578 .enable_mask = BIT(0),
1592 .halt_reg = 0x1194,
1594 .enable_reg = 0x1194,
1595 .enable_mask = BIT(0),
1609 .halt_reg = 0x1198,
1611 .enable_reg = 0x1198,
1612 .enable_mask = BIT(0),
1626 .halt_reg = 0x1174,
1628 .enable_reg = 0x1174,
1629 .enable_mask = BIT(0),
1643 .halt_reg = 0x1178,
1645 .enable_reg = 0x1178,
1646 .enable_mask = BIT(0),
1660 .halt_reg = 0x5298,
1662 .enable_reg = 0x5298,
1663 .enable_mask = BIT(0),
1677 .halt_reg = 0x4028,
1679 .enable_reg = 0x4028,
1680 .enable_mask = BIT(0),
1694 .halt_reg = 0x40b0,
1696 .enable_reg = 0x40b0,
1697 .enable_mask = BIT(0),
1711 .halt_reg = 0x403c,
1713 .enable_reg = 0x403c,
1714 .enable_mask = BIT(0),
1728 .halt_reg = 0x4044,
1730 .enable_reg = 0x4044,
1731 .enable_mask = BIT(0),
1745 .halt_reg = 0x1204,
1747 .enable_reg = 0x1204,
1748 .enable_mask = BIT(0),
1762 .halt_reg = 0x1208,
1764 .enable_reg = 0x1208,
1765 .enable_mask = BIT(0),
1779 .halt_reg = 0x4084,
1781 .enable_reg = 0x4084,
1782 .enable_mask = BIT(0),
1796 .halt_reg = 0x4088,
1798 .enable_reg = 0x4088,
1799 .enable_mask = BIT(0),
1813 .halt_reg = 0x1028,
1815 .enable_reg = 0x1028,
1816 .enable_mask = BIT(0),
1830 .halt_reg = 0x1034,
1832 .enable_reg = 0x1034,
1833 .enable_mask = BIT(0),
1847 .halt_reg = 0x1038,
1849 .enable_reg = 0x1038,
1850 .enable_mask = BIT(0),
1864 .halt_reg = 0x1030,
1866 .enable_reg = 0x1030,
1867 .enable_mask = BIT(0),
1881 .halt_reg = 0x1048,
1883 .enable_reg = 0x1048,
1884 .enable_mask = BIT(0),
1898 .halt_reg = 0x104c,
1900 .enable_reg = 0x104c,
1901 .enable_mask = BIT(0),
1915 .halt_reg = 0x2308,
1917 .enable_reg = 0x2308,
1918 .enable_mask = BIT(0),
1932 .halt_reg = 0x230c,
1934 .enable_reg = 0x230c,
1935 .enable_mask = BIT(0),
1949 .halt_reg = 0x2310,
1951 .enable_reg = 0x2310,
1952 .enable_mask = BIT(0),
1966 .halt_reg = 0x2314,
1968 .enable_reg = 0x2314,
1969 .enable_mask = BIT(0),
1983 .halt_reg = 0x2318,
1985 .enable_reg = 0x2318,
1986 .enable_mask = BIT(0),
2000 .halt_reg = 0x231c,
2002 .enable_reg = 0x231c,
2003 .enable_mask = BIT(0),
2017 .halt_reg = 0x2324,
2019 .enable_reg = 0x2324,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x2328,
2036 .enable_reg = 0x2328,
2037 .enable_mask = BIT(0),
2051 .halt_reg = 0x2338,
2053 .enable_reg = 0x2338,
2054 .enable_mask = BIT(0),
2068 .halt_reg = 0x233c,
2070 .enable_reg = 0x233c,
2071 .enable_mask = BIT(0),
2085 .halt_reg = 0x2340,
2087 .enable_reg = 0x2340,
2088 .enable_mask = BIT(0),
2102 .halt_reg = 0x2344,
2104 .enable_reg = 0x2344,
2105 .enable_mask = BIT(0),
2119 .halt_reg = 0x2348,
2121 .enable_reg = 0x2348,
2122 .enable_mask = BIT(0),
2136 .halt_reg = 0x3484,
2138 .enable_reg = 0x3484,
2139 .enable_mask = BIT(0),
2153 .halt_reg = 0x348c,
2155 .enable_reg = 0x348c,
2156 .enable_mask = BIT(0),
2170 .halt_reg = 0x3494,
2172 .enable_reg = 0x3494,
2173 .enable_mask = BIT(0),
2187 .halt_reg = 0x3444,
2189 .enable_reg = 0x3444,
2190 .enable_mask = BIT(0),
2204 .halt_reg = 0x3474,
2206 .enable_reg = 0x3474,
2207 .enable_mask = BIT(0),
2221 .halt_reg = 0x3384,
2223 .enable_reg = 0x3384,
2224 .enable_mask = BIT(0),
2238 .halt_reg = 0x33b4,
2240 .enable_reg = 0x33b4,
2241 .enable_mask = BIT(0),
2255 .halt_reg = 0x33e4,
2257 .enable_reg = 0x33e4,
2258 .enable_mask = BIT(0),
2272 .halt_reg = 0x3414,
2274 .enable_reg = 0x3414,
2275 .enable_mask = BIT(0),
2289 .halt_reg = 0x3344,
2291 .enable_reg = 0x3344,
2292 .enable_mask = BIT(0),
2306 .halt_reg = 0x3348,
2308 .enable_reg = 0x3348,
2309 .enable_mask = BIT(0),
2323 .halt_reg = 0x3024,
2325 .enable_reg = 0x3024,
2326 .enable_mask = BIT(0),
2340 .halt_reg = 0x3054,
2342 .enable_reg = 0x3054,
2343 .enable_mask = BIT(0),
2357 .halt_reg = 0x3084,
2359 .enable_reg = 0x3084,
2360 .enable_mask = BIT(0),
2374 .halt_reg = 0x3234,
2376 .enable_reg = 0x3234,
2377 .enable_mask = BIT(0),
2391 .halt_reg = 0x3254,
2393 .enable_reg = 0x3254,
2394 .enable_mask = BIT(0),
2408 .halt_reg = 0x3274,
2410 .enable_reg = 0x3274,
2411 .enable_mask = BIT(0),
2425 .halt_reg = 0x35a8,
2427 .enable_reg = 0x35a8,
2428 .enable_mask = BIT(0),
2442 .halt_reg = 0x35b0,
2444 .enable_reg = 0x35b0,
2445 .enable_mask = BIT(0),
2459 .halt_reg = 0x35c0,
2461 .enable_reg = 0x35c0,
2462 .enable_mask = BIT(0),
2476 .halt_reg = 0x35b4,
2478 .enable_reg = 0x35b4,
2479 .enable_mask = BIT(0),
2493 .halt_reg = 0x35b8,
2495 .enable_reg = 0x35b8,
2496 .enable_mask = BIT(0),
2510 .halt_reg = 0x36b8,
2512 .enable_reg = 0x36b8,
2513 .enable_mask = BIT(0),
2527 .halt_reg = 0x36bc,
2529 .enable_reg = 0x36bc,
2530 .enable_mask = BIT(0),
2544 .halt_reg = 0x36a8,
2546 .enable_reg = 0x36a8,
2547 .enable_mask = BIT(0),
2561 .halt_reg = 0x3720,
2563 .enable_reg = 0x3720,
2564 .enable_mask = BIT(0),
2578 .halt_reg = 0x3668,
2580 .enable_reg = 0x3668,
2581 .enable_mask = BIT(0),
2595 .halt_reg = 0x36ac,
2597 .enable_reg = 0x36ac,
2598 .enable_mask = BIT(0),
2612 .halt_reg = 0x3724,
2614 .enable_reg = 0x3724,
2615 .enable_mask = BIT(0),
2629 .halt_reg = 0x3678,
2631 .enable_reg = 0x3678,
2632 .enable_mask = BIT(0),
2646 .halt_reg = 0x3704,
2648 .enable_reg = 0x3704,
2649 .enable_mask = BIT(0),
2663 .halt_reg = 0x3714,
2665 .enable_reg = 0x3714,
2666 .enable_mask = BIT(0),
2680 .halt_reg = 0x36c8,
2682 .enable_reg = 0x36c8,
2683 .enable_mask = BIT(0),
2697 .halt_reg = 0x36c4,
2699 .enable_reg = 0x36c4,
2700 .enable_mask = BIT(0),
2714 .halt_reg = 0x36b0,
2716 .enable_reg = 0x36b0,
2717 .enable_mask = BIT(0),
2731 .halt_reg = 0x36b4,
2733 .enable_reg = 0x36b4,
2734 .enable_mask = BIT(0),
2748 .halt_reg = 0x30b4,
2750 .enable_reg = 0x30b4,
2751 .enable_mask = BIT(0),
2765 .halt_reg = 0x30bc,
2767 .enable_reg = 0x30bc,
2768 .enable_mask = BIT(0),
2782 .halt_reg = 0x30c4,
2784 .enable_reg = 0x30c4,
2785 .enable_mask = BIT(0),
2799 .halt_reg = 0x30d4,
2801 .enable_reg = 0x30d4,
2802 .enable_mask = BIT(0),
2816 .halt_reg = 0x30e4,
2818 .enable_reg = 0x30e4,
2819 .enable_mask = BIT(0),
2833 .halt_reg = 0x3124,
2835 .enable_reg = 0x3124,
2836 .enable_mask = BIT(0),
2850 .halt_reg = 0x3128,
2852 .enable_reg = 0x3128,
2853 .enable_mask = BIT(0),
2867 .halt_reg = 0x3134,
2869 .enable_reg = 0x3134,
2870 .enable_mask = BIT(0),
2884 .halt_reg = 0x3144,
2886 .enable_reg = 0x3144,
2887 .enable_mask = BIT(0),
2901 .halt_reg = 0x3154,
2903 .enable_reg = 0x3154,
2904 .enable_mask = BIT(0),
2918 .halt_reg = 0x3184,
2920 .enable_reg = 0x3184,
2921 .enable_mask = BIT(0),
2935 .halt_reg = 0x3188,
2937 .enable_reg = 0x3188,
2938 .enable_mask = BIT(0),
2952 .halt_reg = 0x3194,
2954 .enable_reg = 0x3194,
2955 .enable_mask = BIT(0),
2969 .halt_reg = 0x31a4,
2971 .enable_reg = 0x31a4,
2972 .enable_mask = BIT(0),
2986 .halt_reg = 0x31b4,
2988 .enable_reg = 0x31b4,
2989 .enable_mask = BIT(0),
3003 .halt_reg = 0x31e4,
3005 .enable_reg = 0x31e4,
3006 .enable_mask = BIT(0),
3020 .halt_reg = 0x31e8,
3022 .enable_reg = 0x31e8,
3023 .enable_mask = BIT(0),
3037 .halt_reg = 0x31f4,
3039 .enable_reg = 0x31f4,
3040 .enable_mask = BIT(0),
3054 .halt_reg = 0x3204,
3056 .enable_reg = 0x3204,
3057 .enable_mask = BIT(0),
3071 .halt_reg = 0x3214,
3073 .enable_reg = 0x3214,
3074 .enable_mask = BIT(0),
3088 .halt_reg = 0x3224,
3090 .enable_reg = 0x3224,
3091 .enable_mask = BIT(0),
3105 .halt_reg = 0x3b68,
3107 .enable_reg = 0x3b68,
3108 .enable_mask = BIT(0),
3122 .halt_reg = 0x3b6c,
3124 .enable_reg = 0x3b6c,
3125 .enable_mask = BIT(0),
3139 .halt_reg = 0x3ba74,
3141 .enable_reg = 0x3ba74,
3142 .enable_mask = BIT(0),
3160 .gdscr = 0x529c,
3169 .gdscr = 0x119c,
3170 .gds_hw_ctrl = 0x120c,
3179 .gdscr = 0x247c,
3180 .gds_hw_ctrl = 0x2480,
3189 .gdscr = 0x3c4c,
3190 .gds_hw_ctrl = 0x3c50,
3199 .gdscr = 0x1024,
3200 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
3210 .gdscr = 0x1040,
3211 .cxcs = (unsigned int []){ 0x1048 },
3222 .gdscr = 0x1044,
3223 .cxcs = (unsigned int []){ 0x104c },
3234 .gdscr = 0x34a0,
3235 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
3245 .gdscr = 0x3664,
3246 .cxcs = (unsigned int []){ 0x36a8 },
3256 .gdscr = 0x3674,
3257 .cxcs = (unsigned int []){ 0x36ac },
3267 .gdscr = 0x35a4,
3268 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3278 .gdscr = 0x36d4,
3279 .cxcs = (unsigned int []){ 0x36b0 },
3289 .gdscr = 0x3b64,
3290 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3300 .gdscr = 0x2304,
3301 .cxcs = (unsigned int []){ 0x2310, 0x231c },
3311 .gdscr = 0x4034,
3312 .gds_hw_ctrl = 0x4038,
3321 .gdscr = 0x4024,
3322 .clamp_io_ctrl = 0x4300,
3323 .cxcs = (unsigned int []){ 0x4028 },
3528 [MMAGICAHB_BCR] = { 0x5020 },
3529 [MMAGIC_CFG_BCR] = { 0x5050 },
3530 [MISC_BCR] = { 0x5010 },
3531 [BTO_BCR] = { 0x5030 },
3532 [MMAGICAXI_BCR] = { 0x5060 },
3533 [MMAGICMAXI_BCR] = { 0x5070 },
3534 [DSA_BCR] = { 0x50a0 },
3535 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3536 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3537 [SMMU_VFE_BCR] = { 0x3c00 },
3538 [SMMU_CPP_BCR] = { 0x3c10 },
3539 [SMMU_JPEG_BCR] = { 0x3c20 },
3540 [MMAGIC_MDSS_BCR] = { 0x2470 },
3541 [THROTTLE_MDSS_BCR] = { 0x2460 },
3542 [SMMU_ROT_BCR] = { 0x2440 },
3543 [SMMU_MDP_BCR] = { 0x2450 },
3544 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3545 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3546 [SMMU_VIDEO_BCR] = { 0x1170 },
3547 [MMAGIC_BIMC_BCR] = { 0x5290 },
3548 [GPU_GX_BCR] = { 0x4020 },
3549 [GPU_BCR] = { 0x4030 },
3550 [GPU_AON_BCR] = { 0x4040 },
3551 [VMEM_BCR] = { 0x1200 },
3552 [MMSS_RBCPR_BCR] = { 0x4080 },
3553 [VIDEO_BCR] = { 0x1020 },
3554 [MDSS_BCR] = { 0x2300 },
3555 [CAMSS_TOP_BCR] = { 0x3480 },
3556 [CAMSS_AHB_BCR] = { 0x3488 },
3557 [CAMSS_MICRO_BCR] = { 0x3490 },
3558 [CAMSS_CCI_BCR] = { 0x3340 },
3559 [CAMSS_PHY0_BCR] = { 0x3020 },
3560 [CAMSS_PHY1_BCR] = { 0x3050 },
3561 [CAMSS_PHY2_BCR] = { 0x3080 },
3562 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3563 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3564 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3565 [CAMSS_JPEG_BCR] = { 0x35a0 },
3566 [CAMSS_VFE_BCR] = { 0x36a0 },
3567 [CAMSS_VFE0_BCR] = { 0x3660 },
3568 [CAMSS_VFE1_BCR] = { 0x3670 },
3569 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3570 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3571 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3572 [CAMSS_CPP_BCR] = { 0x36d0 },
3573 [CAMSS_CSI0_BCR] = { 0x30b0 },
3574 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3575 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3576 [CAMSS_CSI1_BCR] = { 0x3120 },
3577 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3578 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3579 [CAMSS_CSI2_BCR] = { 0x3180 },
3580 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3581 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3582 [CAMSS_CSI3_BCR] = { 0x31e0 },
3583 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3584 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3585 [CAMSS_ISPIF_BCR] = { 0x3220 },
3586 [FD_BCR] = { 0x3b60 },
3587 [MMSS_SPDM_RM_BCR] = { 0x300 },
3594 .max_register = 0xb008,
3625 regmap_update_bits(regmap, 0x50d8, BIT(31), 0); in mmcc_msm8996_probe()
3627 regmap_update_bits(regmap, 0x5054, BIT(15), 0); in mmcc_msm8996_probe()