Lines Matching +full:0 +full:x0210
45 .l_reg = 0x320,
46 .m_reg = 0x324,
47 .n_reg = 0x328,
48 .config_reg = 0x32c,
49 .mode_reg = 0x31c,
50 .status_reg = 0x334,
63 .l_reg = 0x33c,
64 .m_reg = 0x340,
65 .n_reg = 0x344,
66 .config_reg = 0x348,
67 .mode_reg = 0x338,
68 .status_reg = 0x350,
84 .vco_val = 0x2 << 16,
85 .vco_mask = 0x3 << 16,
86 .pre_div_val = 0x0,
88 .post_div_val = 0x0,
89 .post_div_mask = 0x3 << 20,
95 { P_PXO, 0 },
107 { P_PXO, 0 },
121 { P_PXO, 0 },
135 { P_PXO, 0 },
147 { P_PXO, 0 },
168 { 96000000, P_PLL8, 4, 0, 0 },
169 { 128000000, P_PLL8, 3, 0, 0 },
174 .ns_reg = 0x0148,
175 .md_reg = 0x0144,
190 .src_sel_shift = 0,
195 .enable_reg = 0x0140,
207 .halt_reg = 0x01e8,
210 .enable_reg = 0x0140,
211 .enable_mask = BIT(0),
225 .ns_reg = 0x015c,
226 .md_reg = 0x0158,
241 .src_sel_shift = 0,
246 .enable_reg = 0x0154,
258 .halt_reg = 0x01e8,
261 .enable_reg = 0x0154,
262 .enable_mask = BIT(0),
276 .ns_reg = 0x0228,
277 .md_reg = 0x0224,
292 .src_sel_shift = 0,
297 .enable_reg = 0x0220,
309 .halt_reg = 0x01e8,
312 .enable_reg = 0x0220,
313 .enable_mask = BIT(0),
327 { 27000000, P_PXO, 1, 0, 0 },
334 .ns_reg = 0x0048,
335 .md_reg = 0x0044,
349 .src_sel_shift = 0,
354 .enable_reg = 0x0040,
366 .halt_reg = 0x01cc,
369 .enable_reg = 0x0040,
370 .enable_mask = BIT(0),
384 .halt_reg = 0x01e8,
387 .enable_reg = 0x0040,
402 .ns_reg = 0x0010,
403 .md_reg = 0x0028,
417 .src_sel_shift = 0,
422 .enable_reg = 0x0024,
434 .halt_reg = 0x01cc,
437 .enable_reg = 0x0024,
438 .enable_mask = BIT(0),
452 .halt_reg = 0x01e8,
455 .enable_reg = 0x0024,
470 .ns_reg = 0x0234,
471 .md_reg = 0x022c,
485 .src_sel_shift = 0,
490 .enable_reg = 0x022c,
502 .halt_reg = 0x01cc,
505 .enable_reg = 0x022c,
506 .enable_mask = BIT(0),
520 .halt_reg = 0x01e8,
523 .enable_reg = 0x022c,
551 int ret = 0; in pix_rdi_set_parent()
564 for (i = 0; i < num_parents; i++) { in pix_rdi_set_parent()
574 val = 0; in pix_rdi_set_parent()
585 val = 0; in pix_rdi_set_parent()
594 for (i--; i >= 0; i--) { in pix_rdi_set_parent()
616 return 0; in pix_rdi_get_parent()
634 .s_reg = 0x0058,
636 .s2_reg = 0x0238,
639 .enable_reg = 0x0058,
651 .s_reg = 0x0238,
653 .s2_reg = 0x0238,
656 .enable_reg = 0x0238,
668 .s_reg = 0x0058,
670 .s2_reg = 0x0238,
673 .enable_reg = 0x0058,
685 .s_reg = 0x0238,
686 .s_mask = BIT(0),
687 .s2_reg = 0x0238,
690 .enable_reg = 0x0238,
702 .s_reg = 0x0238,
704 .s2_reg = 0x0238,
707 .enable_reg = 0x0238,
725 .ns_reg = 0x0168,
726 .md_reg = 0x0164,
741 .src_sel_shift = 0,
746 .enable_reg = 0x0160,
758 .halt_reg = 0x01e8,
761 .enable_reg = 0x0160,
762 .enable_mask = BIT(0),
776 .halt_reg = 0x01e8,
779 .enable_reg = 0x0160,
794 .halt_reg = 0x01e8,
797 .enable_reg = 0x0160,
812 F_MN( 27000000, P_PXO, 1, 0),
828 .ns_reg[0] = 0x0070,
829 .ns_reg[1] = 0x0070,
830 .md_reg[0] = 0x0064,
831 .md_reg[1] = 0x0068,
832 .bank_reg = 0x0060,
833 .mn[0] = {
849 .s[0] = {
854 .src_sel_shift = 0,
860 .enable_reg = 0x0060,
872 .halt_reg = 0x01c8,
875 .enable_reg = 0x0060,
876 .enable_mask = BIT(0),
890 .ns_reg[0] = 0x007c,
891 .ns_reg[1] = 0x007c,
892 .md_reg[0] = 0x0078,
893 .md_reg[1] = 0x006c,
894 .bank_reg = 0x0074,
895 .mn[0] = {
911 .s[0] = {
916 .src_sel_shift = 0,
922 .enable_reg = 0x0074,
934 .halt_reg = 0x01c8,
937 .enable_reg = 0x0074,
938 .enable_mask = BIT(0),
952 F_MN( 27000000, P_PXO, 1, 0),
972 F_MN( 27000000, P_PXO, 0, 0),
993 .ns_reg[0] = 0x008c,
994 .ns_reg[1] = 0x008c,
995 .md_reg[0] = 0x0084,
996 .md_reg[1] = 0x0088,
997 .bank_reg = 0x0080,
998 .mn[0] = {
1014 .s[0] = {
1019 .src_sel_shift = 0,
1025 .enable_reg = 0x0080,
1044 .halt_reg = 0x01c8,
1047 .enable_reg = 0x0080,
1048 .enable_mask = BIT(0),
1062 F_MN( 27000000, P_PXO, 0, 0),
1073 .ns_reg[0] = 0x021c,
1074 .ns_reg[1] = 0x021c,
1075 .md_reg[0] = 0x01ec,
1076 .md_reg[1] = 0x0218,
1077 .bank_reg = 0x0178,
1078 .mn[0] = {
1094 .s[0] = {
1099 .src_sel_shift = 0,
1105 .enable_reg = 0x0178,
1117 .halt_reg = 0x0240,
1120 .enable_reg = 0x0178,
1121 .enable_mask = BIT(0),
1135 .halt_reg = 0x0240,
1138 .enable_reg = 0x0178,
1153 { 27000000, P_PXO, 1, 0, 0 },
1155 { 54860000, P_PLL8, 7, 0, 0 },
1156 { 96000000, P_PLL8, 4, 0, 0 },
1158 { 128000000, P_PLL8, 3, 0, 0 },
1160 { 200000000, P_PLL2, 4, 0, 0 },
1168 .ns_reg = 0x00a0,
1169 .md_reg = 0x009c,
1183 .src_sel_shift = 0,
1188 .enable_reg = 0x0098,
1200 .halt_reg = 0x01c8,
1203 .enable_reg = 0x0098,
1204 .enable_mask = BIT(0),
1227 .ns_reg = 0x00ac,
1233 .src_sel_shift = 0,
1238 .enable_reg = 0x00a4,
1250 .halt_reg = 0x01c8,
1253 .enable_reg = 0x00a4,
1254 .enable_mask = BIT(0),
1270 { 27000000, P_PXO, 1, 0, 0 },
1288 .ns_reg[0] = 0x00d0,
1289 .ns_reg[1] = 0x00d0,
1290 .md_reg[0] = 0x00c4,
1291 .md_reg[1] = 0x00c8,
1292 .bank_reg = 0x00c0,
1293 .mn[0] = {
1309 .s[0] = {
1314 .src_sel_shift = 0,
1320 .enable_reg = 0x00c0,
1332 .halt_reg = 0x01d0,
1335 .enable_reg = 0x00c0,
1336 .enable_mask = BIT(0),
1350 .halt_reg = 0x01e8,
1353 .enable_reg = 0x016c,
1354 .enable_mask = BIT(0),
1368 .halt_reg = 0x01cc,
1371 .enable_reg = 0x0058,
1403 .ns_reg[0] = 0x00e8,
1404 .ns_reg[1] = 0x00e8,
1405 .bank_reg = 0x00e8,
1406 .p[0] = {
1414 .s[0] = {
1425 .enable_reg = 0x00e0,
1437 .halt_reg = 0x01d0,
1440 .enable_reg = 0x00e0,
1441 .enable_mask = BIT(0),
1455 { P_PXO, 0 },
1470 .ns_reg = 0x00f4,
1471 .md_reg = 0x00f0,
1485 .src_sel_shift = 0,
1490 .enable_reg = 0x00ec,
1503 .halt_reg = 0x01d4,
1506 .enable_reg = 0x00ec,
1521 .halt_reg = 0x01d4,
1524 .enable_reg = 0x00ec,
1539 .halt_reg = 0x01d4,
1542 .enable_reg = 0x00ec,
1543 .enable_mask = BIT(0),
1557 .halt_reg = 0x01d4,
1560 .enable_reg = 0x00ec,
1575 .halt_reg = 0x0240,
1578 .enable_reg = 0x0124,
1593 .halt_reg = 0x0240,
1596 .enable_reg = 0x0124,
1611 .halt_reg = 0x01cc,
1614 .enable_reg = 0x005c,
1628 F_MN( 27000000, P_PXO, 1, 0),
1641 .ns_reg[0] = 0x0100,
1642 .ns_reg[1] = 0x0100,
1643 .md_reg[0] = 0x00fc,
1644 .md_reg[1] = 0x0128,
1645 .bank_reg = 0x00f8,
1646 .mn[0] = {
1662 .s[0] = {
1667 .src_sel_shift = 0,
1673 .enable_reg = 0x00f8,
1685 .halt_reg = 0x01d0,
1688 .enable_reg = 0x00f8,
1689 .enable_mask = BIT(0),
1715 .ns_reg = 0x0118,
1721 .src_sel_shift = 0,
1726 .enable_reg = 0x0110,
1738 .halt_reg = 0x01c8,
1741 .enable_reg = 0x0110,
1742 .enable_mask = BIT(0),
1757 { 27000000, P_PXO, 1, 0, 0 },
1777 .ns_reg = 0x0108,
1791 .src_sel_shift = 0,
1796 .enable_reg = 0x0104,
1808 .halt_reg = 0x01cc,
1811 .enable_reg = 0x0104,
1812 .enable_mask = BIT(0),
1826 .halt_reg = 0x01cc,
1829 .enable_reg = 0x0104,
1844 .halt_reg = 0x01d8,
1847 .enable_reg = 0x0018,
1857 .hwcg_reg = 0x0018,
1859 .halt_reg = 0x01d8,
1862 .enable_reg = 0x0018,
1872 .hwcg_reg = 0x0018,
1874 .halt_reg = 0x01d8,
1877 .enable_reg = 0x0018,
1887 .halt_reg = 0x01d8,
1890 .enable_reg = 0x0018,
1900 .hwcg_reg = 0x0114,
1902 .halt_reg = 0x01e8,
1905 .enable_reg = 0x0114,
1915 .hwcg_reg = 0x0114,
1917 .halt_reg = 0x01e8,
1920 .enable_reg = 0x0114,
1930 .hwcg_reg = 0x0018,
1932 .halt_reg = 0x01d8,
1935 .enable_reg = 0x0018,
1945 .halt_reg = 0x01d8,
1946 .halt_bit = 0,
1948 .enable_reg = 0x0018,
1958 .hwcg_reg = 0x0018,
1960 .halt_reg = 0x01d8,
1963 .enable_reg = 0x0018,
1973 .hwcg_reg = 0x0020,
1975 .halt_reg = 0x01d8,
1978 .enable_reg = 0x0020,
1988 .halt_reg = 0x0240,
1990 .hwcg_reg = 0x0244,
1993 .enable_reg = 0x0244,
2003 .hwcg_reg = 0x0020,
2005 .halt_reg = 0x01d8,
2008 .enable_reg = 0x0020,
2018 .hwcg_reg = 0x0244,
2020 .halt_reg = 0x0240,
2023 .enable_reg = 0x0244,
2033 .halt_reg = 0x01dc,
2036 .enable_reg = 0x0008,
2046 .halt_reg = 0x01dc,
2049 .enable_reg = 0x0008,
2059 .halt_reg = 0x01dc,
2062 .enable_reg = 0x0008,
2072 .hwcg_reg = 0x0038,
2074 .halt_reg = 0x01dc,
2077 .enable_reg = 0x0008,
2087 .halt_reg = 0x01d8,
2090 .enable_reg = 0x0008,
2100 .hwcg_reg = 0x0038,
2102 .halt_reg = 0x01dc,
2105 .enable_reg = 0x0008,
2115 .ns_reg = 0x0054,
2116 .md_reg = 0x0050,
2130 .src_sel_shift = 0,
2134 .enable_reg = 0x004c,
2147 .halt_reg = 0x01d0,
2150 .enable_reg = 0x004c,
2151 .enable_mask = BIT(0),
2165 .ns_reg = 0x012c,
2166 .md_reg = 0x00a8,
2180 .src_sel_shift = 0,
2184 .enable_reg = 0x003c,
2197 .halt_reg = 0x01d0,
2200 .enable_reg = 0x003c,
2201 .enable_mask = BIT(0),
2215 .ns_reg = 0x00b0,
2221 .src_sel_shift = 0,
2225 .enable_reg = 0x0090,
2238 .halt_reg = 0x01cc,
2241 .enable_reg = 0x0090,
2242 .enable_mask = BIT(0),
2256 .ns_reg = 0x012c,
2262 .src_sel_shift = 0,
2266 .enable_reg = 0x0130,
2279 .halt_reg = 0x01cc,
2282 .enable_reg = 0x00b4,
2283 .enable_mask = BIT(0),
2297 .ns_reg = 0x0011c,
2303 .src_sel_shift = 0,
2307 .enable_reg = 0x00cc,
2319 .halt_reg = 0x01e8,
2322 .enable_reg = 0x00cc,
2323 .enable_mask = BIT(0),
2337 .ns_reg = 0x0150,
2343 .src_sel_shift = 0,
2347 .enable_reg = 0x013c,
2359 .halt_reg = 0x01e8,
2362 .enable_reg = 0x013c,
2363 .enable_mask = BIT(0),
2377 .ns_reg = 0x0138,
2378 .md_reg = 0x0134,
2392 .src_sel_shift = 0,
2396 .enable_reg = 0x0130,
2408 .halt_reg = 0x01d0,
2411 .enable_reg = 0x0130,
2412 .enable_mask = BIT(0),
2426 .ns_reg = 0x00e4,
2427 .md_reg = 0x00b8,
2441 .src_sel_shift = 0,
2445 .enable_reg = 0x0094,
2457 .halt_reg = 0x01d0,
2460 .enable_reg = 0x0094,
2461 .enable_mask = BIT(0),
2475 .hwcg_reg = 0x0038,
2477 .halt_reg = 0x01dc,
2480 .enable_reg = 0x0008,
2490 .hwcg_reg = 0x0038,
2492 .halt_reg = 0x01dc,
2495 .enable_reg = 0x0008,
2505 .hwcg_reg = 0x0038,
2507 .halt_reg = 0x01dc,
2510 .enable_reg = 0x0008,
2520 .hwcg_reg = 0x0038,
2522 .halt_reg = 0x01dc,
2525 .enable_reg = 0x0008,
2535 .hwcg_reg = 0x0038,
2537 .halt_reg = 0x01dc,
2540 .enable_reg = 0x0008,
2550 .halt_reg = 0x01dc,
2553 .enable_reg = 0x0008,
2563 .hwcg_reg = 0x0038,
2565 .halt_reg = 0x01dc,
2568 .enable_reg = 0x0008,
2578 .halt_reg = 0x01dc,
2581 .enable_reg = 0x0008,
2591 .halt_reg = 0x01dc,
2594 .enable_reg = 0x0008,
2604 .halt_reg = 0x01dc,
2607 .enable_reg = 0x0008,
2617 .hwcg_reg = 0x0008,
2619 .halt_reg = 0x01dc,
2622 .enable_reg = 0x0008,
2632 .halt_reg = 0x01dc,
2635 .enable_reg = 0x0008,
2645 .halt_reg = 0x0240,
2648 .enable_reg = 0x0248,
2658 .hwcg_reg = 0x0038,
2660 .halt_reg = 0x01dc,
2663 .enable_reg = 0x0008,
2673 .halt_reg = 0x01dc,
2676 .enable_reg = 0x0008,
2686 .halt_reg = 0x01dc,
2689 .enable_reg = 0x0008,
2805 [VPE_AXI_RESET] = { 0x0208, 15 },
2806 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2807 [MPD_AXI_RESET] = { 0x0208, 13 },
2808 [VFE_AXI_RESET] = { 0x0208, 9 },
2809 [SP_AXI_RESET] = { 0x0208, 8 },
2810 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2811 [ROT_AXI_RESET] = { 0x0208, 6 },
2812 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2813 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2814 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2815 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2816 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2817 [FAB_S0_AXI_RESET] = { 0x0208 },
2818 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2819 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2820 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2821 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2822 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2823 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2824 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2825 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2826 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2827 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2828 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2829 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2830 [APU_AHB_RESET] = { 0x020c, 18 },
2831 [CSI_AHB_RESET] = { 0x020c, 17 },
2832 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2833 [VPE_AHB_RESET] = { 0x020c, 14 },
2834 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2835 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2836 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2837 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2838 [HDMI_AHB_RESET] = { 0x020c, 9 },
2839 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2840 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2841 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2842 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2843 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2844 [MDP_AHB_RESET] = { 0x020c, 3 },
2845 [ROT_AHB_RESET] = { 0x020c, 2 },
2846 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2847 [VFE_AHB_RESET] = { 0x020c, 0 },
2848 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2849 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2850 [CSIPHY2_RESET] = { 0x0210, 29 },
2851 [CSI_PIX1_RESET] = { 0x0210, 28 },
2852 [CSIPHY0_RESET] = { 0x0210, 27 },
2853 [CSIPHY1_RESET] = { 0x0210, 26 },
2854 [DSI2_RESET] = { 0x0210, 25 },
2855 [VFE_CSI_RESET] = { 0x0210, 24 },
2856 [MDP_RESET] = { 0x0210, 21 },
2857 [AMP_RESET] = { 0x0210, 20 },
2858 [JPEGD_RESET] = { 0x0210, 19 },
2859 [CSI1_RESET] = { 0x0210, 18 },
2860 [VPE_RESET] = { 0x0210, 17 },
2861 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2862 [VFE_RESET] = { 0x0210, 15 },
2863 [GFX2D0_RESET] = { 0x0210, 14 },
2864 [GFX2D1_RESET] = { 0x0210, 13 },
2865 [GFX3D_RESET] = { 0x0210, 12 },
2866 [HDMI_RESET] = { 0x0210, 11 },
2867 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2868 [IJPEG_RESET] = { 0x0210, 9 },
2869 [CSI0_RESET] = { 0x0210, 8 },
2870 [DSI_RESET] = { 0x0210, 7 },
2871 [VCODEC_RESET] = { 0x0210, 6 },
2872 [MDP_TV_RESET] = { 0x0210, 4 },
2873 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2874 [ROT_RESET] = { 0x0210, 2 },
2875 [TV_HDMI_RESET] = { 0x0210, 1 },
2876 [TV_ENC_RESET] = { 0x0210 },
2877 [CSI2_RESET] = { 0x0214, 2 },
2878 [CSI_RDI1_RESET] = { 0x0214, 1 },
2879 [CSI_RDI2_RESET] = { 0x0214 },
2989 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2990 [VCAP_AXI_RESET] = { 0x0208, 16 },
2991 [VPE_AXI_RESET] = { 0x0208, 15 },
2992 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2993 [MPD_AXI_RESET] = { 0x0208, 13 },
2994 [VFE_AXI_RESET] = { 0x0208, 9 },
2995 [SP_AXI_RESET] = { 0x0208, 8 },
2996 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2997 [ROT_AXI_RESET] = { 0x0208, 6 },
2998 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2999 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
3000 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
3001 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
3002 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
3003 [FAB_S0_AXI_RESET] = { 0x0208 },
3004 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
3005 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
3006 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
3007 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
3008 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
3009 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
3010 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
3011 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
3012 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
3013 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
3014 [APU_AHB_RESET] = { 0x020c, 18 },
3015 [CSI_AHB_RESET] = { 0x020c, 17 },
3016 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
3017 [VPE_AHB_RESET] = { 0x020c, 14 },
3018 [FABRIC_AHB_RESET] = { 0x020c, 13 },
3019 [GFX3D_AHB_RESET] = { 0x020c, 10 },
3020 [HDMI_AHB_RESET] = { 0x020c, 9 },
3021 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
3022 [IJPEG_AHB_RESET] = { 0x020c, 7 },
3023 [DSI_M_AHB_RESET] = { 0x020c, 6 },
3024 [DSI_S_AHB_RESET] = { 0x020c, 5 },
3025 [JPEGD_AHB_RESET] = { 0x020c, 4 },
3026 [MDP_AHB_RESET] = { 0x020c, 3 },
3027 [ROT_AHB_RESET] = { 0x020c, 2 },
3028 [VCODEC_AHB_RESET] = { 0x020c, 1 },
3029 [VFE_AHB_RESET] = { 0x020c, 0 },
3030 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
3031 [VCAP_AHB_RESET] = { 0x0200, 2 },
3032 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
3033 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
3034 [CSIPHY2_RESET] = { 0x0210, 31 },
3035 [CSI_PIX1_RESET] = { 0x0210, 30 },
3036 [CSIPHY0_RESET] = { 0x0210, 29 },
3037 [CSIPHY1_RESET] = { 0x0210, 28 },
3038 [CSI_RDI_RESET] = { 0x0210, 27 },
3039 [CSI_PIX_RESET] = { 0x0210, 26 },
3040 [DSI2_RESET] = { 0x0210, 25 },
3041 [VFE_CSI_RESET] = { 0x0210, 24 },
3042 [MDP_RESET] = { 0x0210, 21 },
3043 [AMP_RESET] = { 0x0210, 20 },
3044 [JPEGD_RESET] = { 0x0210, 19 },
3045 [CSI1_RESET] = { 0x0210, 18 },
3046 [VPE_RESET] = { 0x0210, 17 },
3047 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
3048 [VFE_RESET] = { 0x0210, 15 },
3049 [GFX3D_RESET] = { 0x0210, 12 },
3050 [HDMI_RESET] = { 0x0210, 11 },
3051 [MMSS_IMEM_RESET] = { 0x0210, 10 },
3052 [IJPEG_RESET] = { 0x0210, 9 },
3053 [CSI0_RESET] = { 0x0210, 8 },
3054 [DSI_RESET] = { 0x0210, 7 },
3055 [VCODEC_RESET] = { 0x0210, 6 },
3056 [MDP_TV_RESET] = { 0x0210, 4 },
3057 [MDP_VSYNC_RESET] = { 0x0210, 3 },
3058 [ROT_RESET] = { 0x0210, 2 },
3059 [TV_HDMI_RESET] = { 0x0210, 1 },
3060 [VCAP_NPL_RESET] = { 0x0214, 4 },
3061 [VCAP_RESET] = { 0x0214, 3 },
3062 [CSI2_RESET] = { 0x0214, 2 },
3063 [CSI_RDI1_RESET] = { 0x0214, 1 },
3064 [CSI_RDI2_RESET] = { 0x0214 },
3071 .max_register = 0x334,
3079 .max_register = 0x350,
3115 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map; in mmcc_msm8960_probe()