Lines Matching +full:power +full:- +full:off +full:- +full:delay +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
16 #include <linux/reset-controller.h>
41 /* Transition delay shifts */
66 if (sc->flags & POLL_CFG_GDSCR) in gdsc_check_status()
67 reg = sc->gdscr + CFG_GDSCR_OFFSET; in gdsc_check_status()
68 else if (sc->gds_hw_ctrl) in gdsc_check_status()
69 reg = sc->gds_hw_ctrl; in gdsc_check_status()
71 reg = sc->gdscr; in gdsc_check_status()
73 ret = regmap_read(sc->regmap, reg, &val); in gdsc_check_status()
77 if (sc->flags & POLL_CFG_GDSCR) { in gdsc_check_status()
93 return -EINVAL; in gdsc_check_status()
100 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); in gdsc_hwctrl()
116 return -ETIMEDOUT; in gdsc_poll_status()
124 if (sc->collapse_mask) { in gdsc_update_collapse_bit()
125 reg = sc->collapse_ctrl; in gdsc_update_collapse_bit()
126 mask = sc->collapse_mask; in gdsc_update_collapse_bit()
128 reg = sc->gdscr; in gdsc_update_collapse_bit()
132 ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0); in gdsc_update_collapse_bit()
144 if (status == GDSC_ON && sc->rsupply) { in gdsc_toggle_logic()
145 ret = regulator_enable(sc->rsupply); in gdsc_toggle_logic()
153 if ((sc->flags & VOTABLE) && status == GDSC_OFF && !wait) { in gdsc_toggle_logic()
155 * Add a short delay here to ensure that an enable in gdsc_toggle_logic()
163 if (sc->gds_hw_ctrl) { in gdsc_toggle_logic()
165 * The gds hw controller asserts/de-asserts the status bit soon in gdsc_toggle_logic()
166 * after it receives a power on/off request from a master. in gdsc_toggle_logic()
171 * Add a delay of 1 us between writing to the SW_COLLAPSE bit in gdsc_toggle_logic()
178 WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n"); in gdsc_toggle_logic()
180 if (!ret && status == GDSC_OFF && sc->rsupply) { in gdsc_toggle_logic()
181 ret = regulator_disable(sc->rsupply); in gdsc_toggle_logic()
193 for (i = 0; i < sc->reset_count; i++) in gdsc_deassert_reset()
194 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]); in gdsc_deassert_reset()
202 for (i = 0; i < sc->reset_count; i++) in gdsc_assert_reset()
203 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]); in gdsc_assert_reset()
212 if (!(sc->flags & NO_RET_PERIPH)) in gdsc_force_mem_on()
215 for (i = 0; i < sc->cxc_count; i++) in gdsc_force_mem_on()
216 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask); in gdsc_force_mem_on()
224 if (!(sc->flags & NO_RET_PERIPH)) in gdsc_clear_mem_on()
227 for (i = 0; i < sc->cxc_count; i++) in gdsc_clear_mem_on()
228 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0); in gdsc_clear_mem_on()
233 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, in gdsc_deassert_clamp_io()
239 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, in gdsc_assert_clamp_io()
245 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, in gdsc_assert_reset_aon()
248 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl, in gdsc_assert_reset_aon()
256 regmap_update_bits(sc->regmap, sc->gdscr, mask, mask); in gdsc_retain_ff_on()
264 if (sc->pwrsts == PWRSTS_ON) in gdsc_enable()
267 if (sc->flags & SW_RESET) { in gdsc_enable()
273 if (sc->flags & CLAMP_IO) { in gdsc_enable()
274 if (sc->flags & AON_RESET) in gdsc_enable()
283 if (sc->pwrsts & PWRSTS_OFF) in gdsc_enable()
287 * If clocks to this power domain were already on, they will take an in gdsc_enable()
288 * additional 4 clock cycles to re-enable after the power domain is in gdsc_enable()
289 * enabled. Delay to account for this. A delay is also needed to ensure in gdsc_enable()
290 * clocks are not enabled within 400ns of enabling power to the in gdsc_enable()
296 if (sc->flags & HW_CTRL) { in gdsc_enable()
301 * Wait for the GDSC to go through a power down and in gdsc_enable()
304 * the GDSC can finish the power cycle. in gdsc_enable()
305 * We wait 1us before returning to ensure the firmware in gdsc_enable()
311 if (sc->flags & RETAIN_FF_ENABLE) in gdsc_enable()
322 if (sc->pwrsts == PWRSTS_ON) in gdsc_disable()
325 /* Turn off HW trigger mode if supported */ in gdsc_disable()
326 if (sc->flags & HW_CTRL) { in gdsc_disable()
331 * Wait for the GDSC to go through a power down and in gdsc_disable()
333 * bits for the gdsc before the power cycle is completed in gdsc_disable()
343 if (sc->pwrsts & PWRSTS_OFF) in gdsc_disable()
351 * domain goes down to a Low power state in gdsc_disable()
353 if (sc->pwrsts == PWRSTS_RET_ON) in gdsc_disable()
356 ret = gdsc_toggle_logic(sc, GDSC_OFF, domain->synced_poweroff); in gdsc_disable()
360 if (sc->flags & CLAMP_IO) in gdsc_disable()
376 * Wait for the GDSC to go through a power down and in gdsc_set_hwmode()
378 * power cycle is finished we might read incorrect values. in gdsc_set_hwmode()
385 * again, hence we need to poll for GDSC to complete the power up. in gdsc_set_hwmode()
398 regmap_read(sc->regmap, sc->gdscr, &val); in gdsc_get_hwmode()
410 * Disable SW override: Use hardware state-machine for sequencing. in gdsc_init()
416 if (!sc->en_rest_wait_val) in gdsc_init()
417 sc->en_rest_wait_val = EN_REST_WAIT_VAL; in gdsc_init()
418 if (!sc->en_few_wait_val) in gdsc_init()
419 sc->en_few_wait_val = EN_FEW_WAIT_VAL; in gdsc_init()
420 if (!sc->clk_dis_wait_val) in gdsc_init()
421 sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL; in gdsc_init()
423 val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT | in gdsc_init()
424 sc->en_few_wait_val << EN_FEW_WAIT_SHIFT | in gdsc_init()
425 sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT; in gdsc_init()
427 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); in gdsc_init()
432 if (sc->pwrsts == PWRSTS_ON) { in gdsc_init()
444 if (sc->rsupply) { in gdsc_init()
445 ret = regulator_enable(sc->rsupply); in gdsc_init()
454 if (sc->flags & VOTABLE) { in gdsc_init()
461 if (sc->flags & HW_CTRL) { in gdsc_init()
469 * otherwise we end up turning off the GDSC and destroying all in gdsc_init()
472 if (sc->flags & RETAIN_FF_ENABLE) in gdsc_init()
474 } else if (sc->flags & ALWAYS_ON) { in gdsc_init()
476 gdsc_enable(&sc->pd); in gdsc_init()
480 if (on || (sc->pwrsts & PWRSTS_RET)) in gdsc_init()
485 if (sc->flags & ALWAYS_ON) in gdsc_init()
486 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON; in gdsc_init()
487 if (!sc->pd.power_off) in gdsc_init()
488 sc->pd.power_off = gdsc_disable; in gdsc_init()
489 if (!sc->pd.power_on) in gdsc_init()
490 sc->pd.power_on = gdsc_enable; in gdsc_init()
491 if (sc->flags & HW_CTRL_TRIGGER) { in gdsc_init()
492 sc->pd.set_hwmode_dev = gdsc_set_hwmode; in gdsc_init()
493 sc->pd.get_hwmode_dev = gdsc_get_hwmode; in gdsc_init()
496 ret = pm_genpd_init(&sc->pd, NULL, !on); in gdsc_init()
503 if (on && sc->rsupply) in gdsc_init()
504 regulator_disable(sc->rsupply); in gdsc_init()
514 struct device *dev = desc->dev; in gdsc_register()
515 struct gdsc **scs = desc->scs; in gdsc_register()
516 size_t num = desc->num; in gdsc_register()
520 return -ENOMEM; in gdsc_register()
522 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains), in gdsc_register()
524 if (!data->domains) in gdsc_register()
525 return -ENOMEM; in gdsc_register()
528 if (!scs[i] || !scs[i]->supply) in gdsc_register()
531 scs[i]->rsupply = devm_regulator_get_optional(dev, scs[i]->supply); in gdsc_register()
532 if (IS_ERR(scs[i]->rsupply)) { in gdsc_register()
533 ret = PTR_ERR(scs[i]->rsupply); in gdsc_register()
534 if (ret != -ENODEV) in gdsc_register()
537 scs[i]->rsupply = NULL; in gdsc_register()
541 data->num_domains = num; in gdsc_register()
545 scs[i]->regmap = regmap; in gdsc_register()
546 scs[i]->rcdev = rcdev; in gdsc_register()
550 data->domains[i] = &scs[i]->pd; in gdsc_register()
557 if (scs[i]->parent) in gdsc_register()
558 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); in gdsc_register()
559 else if (!IS_ERR_OR_NULL(dev->pm_domain)) in gdsc_register()
560 pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); in gdsc_register()
563 return of_genpd_add_provider_onecell(dev->of_node, data); in gdsc_register()
569 struct device *dev = desc->dev; in gdsc_unregister()
570 struct gdsc **scs = desc->scs; in gdsc_unregister()
571 size_t num = desc->num; in gdsc_unregister()
577 if (scs[i]->parent) in gdsc_unregister()
578 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); in gdsc_unregister()
579 else if (!IS_ERR_OR_NULL(dev->pm_domain)) in gdsc_unregister()
580 pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); in gdsc_unregister()
582 of_genpd_del_provider(dev->of_node); in gdsc_unregister()
595 * ensure that the GX is off during this super special case. We do this by
599 * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
600 * driver. During power up, nothing will happen from the CPU (and the GMU will
601 * power up normally but during power down this will ensure that the GX domain
602 * is *really* off - this gives us a semi standard way of doing what we need.
610 if (sc->rsupply) in gdsc_gx_do_nothing_enable()
611 ret = regulator_enable(sc->rsupply); in gdsc_gx_do_nothing_enable()