Lines Matching +full:0 +full:x12010
52 .offset = 0x0,
55 .enable_reg = 0x52030,
56 .enable_mask = BIT(0),
69 { 0x1, 2 },
74 .offset = 0x0,
91 .offset = 0x4000,
94 .enable_reg = 0x52030,
108 .offset = 0x7000,
111 .enable_reg = 0x52030,
125 .offset = 0x8000,
128 .enable_reg = 0x52030,
142 .offset = 0x9000,
145 .enable_reg = 0x52030,
159 { P_BI_TCXO, 0 },
171 { P_BI_TCXO, 0 },
181 { P_BI_TCXO, 0 },
195 { P_BI_TCXO, 0 },
203 { P_BI_TCXO, 0 },
217 { P_BI_TCXO, 0 },
231 { P_BI_TCXO, 0 },
243 { P_BI_TCXO, 0 },
257 { P_BI_TCXO, 0 },
271 { P_BI_TCXO, 0 },
284 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
294 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
304 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
317 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
318 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
319 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
324 .cmd_rcgr = 0x64004,
339 .cmd_rcgr = 0x65004,
354 .cmd_rcgr = 0x66004,
369 F(19200000, P_BI_TCXO, 1, 0, 0),
374 .cmd_rcgr = 0xa0180,
389 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
394 .cmd_rcgr = 0xa0054,
395 .mnd_width = 0,
409 .cmd_rcgr = 0x2c180,
424 .cmd_rcgr = 0x2c054,
425 .mnd_width = 0,
439 .cmd_rcgr = 0x13180,
454 .cmd_rcgr = 0x13054,
455 .mnd_width = 0,
469 .cmd_rcgr = 0x5808c,
484 .cmd_rcgr = 0x58070,
485 .mnd_width = 0,
499 .cmd_rcgr = 0x6b080,
514 .cmd_rcgr = 0x6b064,
515 .mnd_width = 0,
529 .cmd_rcgr = 0x2f080,
544 .cmd_rcgr = 0x2f064,
545 .mnd_width = 0,
559 .cmd_rcgr = 0x3108c,
574 .cmd_rcgr = 0x31070,
575 .mnd_width = 0,
589 .cmd_rcgr = 0x8d08c,
604 .cmd_rcgr = 0x8d070,
605 .mnd_width = 0,
619 .cmd_rcgr = 0xa400c,
620 .mnd_width = 0,
634 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
639 .cmd_rcgr = 0x33010,
640 .mnd_width = 0,
656 F(19200000, P_BI_TCXO, 1, 0, 0),
661 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
664 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
677 .cmd_rcgr = 0x42010,
694 .cmd_rcgr = 0x42148,
705 F(19200000, P_BI_TCXO, 1, 0, 0),
712 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
713 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
726 .cmd_rcgr = 0x42288,
743 .cmd_rcgr = 0x423c8,
754 F(19200000, P_BI_TCXO, 1, 0, 0),
759 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
762 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
775 .cmd_rcgr = 0x42500,
792 .cmd_rcgr = 0x42638,
809 .cmd_rcgr = 0x42770,
826 .cmd_rcgr = 0x428a8,
843 .cmd_rcgr = 0x18010,
860 .cmd_rcgr = 0x18148,
877 .cmd_rcgr = 0x18288,
894 .cmd_rcgr = 0x183c8,
911 .cmd_rcgr = 0x18500,
928 .cmd_rcgr = 0x18638,
945 .cmd_rcgr = 0x18770,
962 .cmd_rcgr = 0x188a8,
979 .cmd_rcgr = 0x1e010,
996 .cmd_rcgr = 0x1e148,
1013 .cmd_rcgr = 0x1e288,
1030 .cmd_rcgr = 0x1e3c8,
1047 .cmd_rcgr = 0x1e500,
1064 .cmd_rcgr = 0x1e638,
1081 .cmd_rcgr = 0x1e770,
1098 .cmd_rcgr = 0x1e8a8,
1108 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1109 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1110 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1111 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1116 .cmd_rcgr = 0x14018,
1132 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1133 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1138 .cmd_rcgr = 0x16018,
1153 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1154 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1155 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1156 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1161 .cmd_rcgr = 0x77030,
1176 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1177 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1178 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1183 .cmd_rcgr = 0x77080,
1184 .mnd_width = 0,
1198 .cmd_rcgr = 0x770b4,
1199 .mnd_width = 0,
1213 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1214 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1215 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1220 .cmd_rcgr = 0x77098,
1221 .mnd_width = 0,
1235 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1236 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1241 .cmd_rcgr = 0x2902c,
1256 .cmd_rcgr = 0x29158,
1257 .mnd_width = 0,
1271 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1272 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1273 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1274 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1279 .cmd_rcgr = 0x1702c,
1294 .cmd_rcgr = 0x17158,
1295 .mnd_width = 0,
1309 .cmd_rcgr = 0x3902c,
1324 .cmd_rcgr = 0x39044,
1325 .mnd_width = 0,
1339 .cmd_rcgr = 0xa102c,
1354 .cmd_rcgr = 0xa1044,
1355 .mnd_width = 0,
1369 .cmd_rcgr = 0xa202c,
1384 .cmd_rcgr = 0xa2044,
1385 .mnd_width = 0,
1399 .cmd_rcgr = 0x172a0,
1400 .mnd_width = 0,
1414 .cmd_rcgr = 0x39074,
1415 .mnd_width = 0,
1429 .cmd_rcgr = 0xa1074,
1430 .mnd_width = 0,
1444 .cmd_rcgr = 0xa2074,
1445 .mnd_width = 0,
1459 F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
1460 F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
1461 F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
1466 .cmd_rcgr = 0x9f024,
1481 F(19200000, P_BI_TCXO, 1, 0, 0),
1482 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
1483 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1488 .cmd_rcgr = 0x9f0e8,
1489 .mnd_width = 0,
1503 .cmd_rcgr = 0x9f08c,
1504 .mnd_width = 0,
1518 F(19200000, P_BI_TCXO, 1, 0, 0),
1519 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1524 .cmd_rcgr = 0x9f070,
1525 .mnd_width = 0,
1539 .cmd_rcgr = 0x2b024,
1554 .cmd_rcgr = 0x2b0e8,
1555 .mnd_width = 0,
1569 .cmd_rcgr = 0x2b08c,
1570 .mnd_width = 0,
1584 .cmd_rcgr = 0x2b070,
1585 .mnd_width = 0,
1599 .cmd_rcgr = 0x11024,
1614 .cmd_rcgr = 0x110e8,
1615 .mnd_width = 0,
1629 .cmd_rcgr = 0x1108c,
1630 .mnd_width = 0,
1644 .cmd_rcgr = 0x11070,
1645 .mnd_width = 0,
1659 .reg = 0x58088,
1673 .reg = 0x5806c,
1674 .shift = 0,
1687 .reg = 0x6b07c,
1701 .reg = 0x6b060,
1702 .shift = 0,
1715 .reg = 0x2f07c,
1729 .reg = 0x2f060,
1730 .shift = 0,
1743 .reg = 0x31088,
1757 .reg = 0x3106c,
1758 .shift = 0,
1771 .reg = 0x8d088,
1785 .reg = 0x8d06c,
1786 .shift = 0,
1799 .reg = 0x42284,
1800 .shift = 0,
1814 .reg = 0x423c4,
1815 .shift = 0,
1829 .reg = 0x18284,
1830 .shift = 0,
1844 .reg = 0x183c4,
1845 .shift = 0,
1859 .reg = 0x1e284,
1860 .shift = 0,
1874 .reg = 0x1e3c4,
1875 .shift = 0,
1889 .reg = 0x29284,
1890 .shift = 0,
1904 .reg = 0x17284,
1905 .shift = 0,
1919 .reg = 0x3905c,
1920 .shift = 0,
1934 .reg = 0xa105c,
1935 .shift = 0,
1949 .reg = 0xa205c,
1950 .shift = 0,
1964 .halt_reg = 0x2d17c,
1966 .hwcg_reg = 0x2d17c,
1969 .enable_reg = 0x2d17c,
1970 .enable_mask = BIT(0),
1979 .halt_reg = 0x2d174,
1981 .hwcg_reg = 0x2d174,
1984 .enable_reg = 0x2d174,
1985 .enable_mask = BIT(0),
1994 .halt_reg = 0x770e4,
1996 .hwcg_reg = 0x770e4,
1999 .enable_reg = 0x770e4,
2000 .enable_mask = BIT(0),
2014 .halt_reg = 0x2928c,
2016 .hwcg_reg = 0x2928c,
2019 .enable_reg = 0x2928c,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x173d0,
2036 .hwcg_reg = 0x173d0,
2039 .enable_reg = 0x173d0,
2040 .enable_mask = BIT(0),
2054 .halt_reg = 0x39090,
2056 .hwcg_reg = 0x39090,
2059 .enable_reg = 0x39090,
2060 .enable_mask = BIT(0),
2074 .halt_reg = 0xa1090,
2076 .hwcg_reg = 0xa1090,
2079 .enable_reg = 0xa1090,
2080 .enable_mask = BIT(0),
2094 .halt_reg = 0xa2090,
2096 .hwcg_reg = 0xa2090,
2099 .enable_reg = 0xa2090,
2100 .enable_mask = BIT(0),
2114 .halt_reg = 0x9f118,
2116 .hwcg_reg = 0x9f118,
2119 .enable_reg = 0x9f118,
2120 .enable_mask = BIT(0),
2134 .halt_reg = 0x2b118,
2136 .hwcg_reg = 0x2b118,
2139 .enable_reg = 0x2b118,
2140 .enable_mask = BIT(0),
2154 .halt_reg = 0x11118,
2156 .hwcg_reg = 0x11118,
2159 .enable_reg = 0x11118,
2160 .enable_mask = BIT(0),
2174 .halt_reg = 0x2d034,
2176 .hwcg_reg = 0x2d034,
2179 .enable_reg = 0x2d034,
2180 .enable_mask = BIT(0),
2189 .halt_reg = 0x4a004,
2191 .hwcg_reg = 0x4a004,
2194 .enable_reg = 0x4a004,
2195 .enable_mask = BIT(0),
2204 .halt_reg = 0x4a008,
2206 .hwcg_reg = 0x4a008,
2209 .enable_reg = 0x4a008,
2210 .enable_mask = BIT(0),
2219 .halt_reg = 0x4a014,
2222 .enable_reg = 0x4a014,
2223 .enable_mask = BIT(0),
2232 .halt_reg = 0x38004,
2234 .hwcg_reg = 0x38004,
2237 .enable_reg = 0x52000,
2247 .halt_reg = 0x26010,
2249 .hwcg_reg = 0x26010,
2252 .enable_reg = 0x26010,
2253 .enable_mask = BIT(0),
2262 .halt_reg = 0x2601c,
2264 .hwcg_reg = 0x2601c,
2267 .enable_reg = 0x2601c,
2268 .enable_mask = BIT(0),
2277 .halt_reg = 0x10028,
2279 .hwcg_reg = 0x10028,
2282 .enable_reg = 0x52028,
2292 .halt_reg = 0x1002c,
2294 .hwcg_reg = 0x1002c,
2297 .enable_reg = 0x52028,
2307 .halt_reg = 0x10030,
2309 .hwcg_reg = 0x10030,
2312 .enable_reg = 0x52000,
2322 .halt_reg = 0x29288,
2324 .hwcg_reg = 0x29288,
2327 .enable_reg = 0x29288,
2328 .enable_mask = BIT(0),
2342 .halt_reg = 0x173cc,
2344 .hwcg_reg = 0x173cc,
2347 .enable_reg = 0x173cc,
2348 .enable_mask = BIT(0),
2362 .halt_reg = 0x3908c,
2364 .hwcg_reg = 0x3908c,
2367 .enable_reg = 0x3908c,
2368 .enable_mask = BIT(0),
2382 .halt_reg = 0xa108c,
2384 .hwcg_reg = 0xa108c,
2387 .enable_reg = 0xa108c,
2388 .enable_mask = BIT(0),
2402 .halt_reg = 0xa208c,
2404 .hwcg_reg = 0xa208c,
2407 .enable_reg = 0xa208c,
2408 .enable_mask = BIT(0),
2422 .halt_reg = 0x2d024,
2424 .hwcg_reg = 0x2d024,
2427 .enable_reg = 0x52028,
2437 .halt_reg = 0x2d028,
2439 .hwcg_reg = 0x2d028,
2442 .enable_reg = 0x52028,
2452 .halt_reg = 0x2d02c,
2454 .hwcg_reg = 0x2d02c,
2457 .enable_reg = 0x52018,
2467 .halt_reg = 0x2c2b4,
2470 .enable_reg = 0x52010,
2480 .halt_reg = 0x132b4,
2483 .enable_reg = 0x52010,
2493 .halt_reg = 0x10014,
2495 .hwcg_reg = 0x10014,
2498 .enable_reg = 0x52008,
2508 .halt_reg = 0x10018,
2510 .hwcg_reg = 0x10018,
2513 .enable_reg = 0x52028,
2523 .halt_reg = 0xa02b4,
2525 .hwcg_reg = 0xa02b4,
2528 .enable_reg = 0x52010,
2538 .halt_reg = 0x7115c,
2540 .hwcg_reg = 0x7115c,
2543 .enable_reg = 0x7115c,
2544 .enable_mask = BIT(0),
2553 .halt_reg = 0x2700c,
2555 .hwcg_reg = 0x2700c,
2558 .enable_reg = 0x2700c,
2559 .enable_mask = BIT(0),
2568 .halt_reg = 0x27018,
2571 .enable_reg = 0x27018,
2572 .enable_mask = BIT(0),
2581 .halt_reg = 0x64000,
2584 .enable_reg = 0x64000,
2585 .enable_mask = BIT(0),
2599 .halt_reg = 0x65000,
2602 .enable_reg = 0x65000,
2603 .enable_mask = BIT(0),
2617 .halt_reg = 0x66000,
2620 .enable_reg = 0x66000,
2621 .enable_mask = BIT(0),
2635 .halt_reg = 0x71004,
2637 .hwcg_reg = 0x71004,
2640 .enable_reg = 0x71004,
2641 .enable_mask = BIT(0),
2652 .enable_reg = 0x52000,
2669 .enable_reg = 0x52000,
2684 .halt_reg = 0x71010,
2686 .hwcg_reg = 0x71010,
2689 .enable_reg = 0x71010,
2690 .enable_mask = BIT(0),
2699 .halt_reg = 0x71018,
2702 .enable_reg = 0x71018,
2703 .enable_mask = BIT(0),
2712 .halt_reg = 0xa0050,
2715 .enable_reg = 0x52010,
2730 .halt_reg = 0x2c050,
2733 .enable_reg = 0x52020,
2748 .halt_reg = 0x13050,
2751 .enable_reg = 0x52020,
2766 .halt_reg = 0xa0038,
2769 .enable_reg = 0x52010,
2784 .halt_reg = 0xa0034,
2786 .hwcg_reg = 0xa0034,
2789 .enable_reg = 0x52010,
2799 .halt_reg = 0xa0028,
2801 .hwcg_reg = 0xa0028,
2804 .enable_reg = 0x52010,
2814 .halt_reg = 0xa0044,
2817 .enable_reg = 0x52010,
2827 .halt_reg = 0xa001c,
2829 .hwcg_reg = 0xa001c,
2832 .enable_reg = 0x52010,
2842 .halt_reg = 0xa0018,
2845 .enable_reg = 0x52010,
2855 .halt_reg = 0x2c038,
2858 .enable_reg = 0x52020,
2873 .halt_reg = 0x2c034,
2875 .hwcg_reg = 0x2c034,
2878 .enable_reg = 0x52020,
2888 .halt_reg = 0x2c028,
2890 .hwcg_reg = 0x2c028,
2893 .enable_reg = 0x52020,
2903 .halt_reg = 0x2c044,
2906 .enable_reg = 0x52020,
2916 .halt_reg = 0x2c01c,
2918 .hwcg_reg = 0x2c01c,
2921 .enable_reg = 0x52020,
2931 .halt_reg = 0x2c018,
2934 .enable_reg = 0x52020,
2944 .halt_reg = 0x13038,
2947 .enable_reg = 0x52020,
2962 .halt_reg = 0x13034,
2964 .hwcg_reg = 0x13034,
2967 .enable_reg = 0x52020,
2977 .halt_reg = 0x13028,
2979 .hwcg_reg = 0x13028,
2982 .enable_reg = 0x52020,
2992 .halt_reg = 0x13044,
2995 .enable_reg = 0x52020,
3005 .halt_reg = 0x1301c,
3007 .hwcg_reg = 0x1301c,
3010 .enable_reg = 0x52020,
3020 .halt_reg = 0x13018,
3023 .enable_reg = 0x52020,
3033 .halt_reg = 0x58038,
3036 .enable_reg = 0x52020,
3051 .halt_reg = 0x58034,
3053 .hwcg_reg = 0x58034,
3056 .enable_reg = 0x52020,
3057 .enable_mask = BIT(0),
3066 .halt_reg = 0x58028,
3068 .hwcg_reg = 0x58028,
3071 .enable_reg = 0x52018,
3081 .halt_reg = 0x58044,
3084 .enable_reg = 0x52020,
3094 .halt_reg = 0x5805c,
3097 .enable_reg = 0x52020,
3112 .halt_reg = 0x58050,
3115 .enable_reg = 0x52020,
3125 .halt_reg = 0x58060,
3128 .enable_reg = 0x52020,
3143 .halt_reg = 0x5801c,
3145 .hwcg_reg = 0x5801c,
3148 .enable_reg = 0x52018,
3158 .halt_reg = 0x58018,
3161 .enable_reg = 0x52018,
3171 .halt_reg = 0x6b038,
3174 .enable_reg = 0x52008,
3189 .halt_reg = 0x6b034,
3191 .hwcg_reg = 0x6b034,
3194 .enable_reg = 0x52008,
3204 .halt_reg = 0x6b028,
3206 .hwcg_reg = 0x6b028,
3209 .enable_reg = 0x52008,
3219 .halt_reg = 0x6b050,
3222 .enable_reg = 0x52000,
3237 .halt_reg = 0x6b044,
3240 .enable_reg = 0x52008,
3250 .halt_reg = 0x6b054,
3253 .enable_reg = 0x52010,
3268 .halt_reg = 0x6b01c,
3270 .hwcg_reg = 0x6b01c,
3273 .enable_reg = 0x52008,
3274 .enable_mask = BIT(0),
3283 .halt_reg = 0x6b018,
3286 .enable_reg = 0x52008,
3296 .halt_reg = 0x2f038,
3299 .enable_reg = 0x52018,
3314 .halt_reg = 0x2f034,
3316 .hwcg_reg = 0x2f034,
3319 .enable_reg = 0x52018,
3329 .halt_reg = 0x2f028,
3331 .hwcg_reg = 0x2f028,
3334 .enable_reg = 0x52018,
3344 .halt_reg = 0x2f050,
3347 .enable_reg = 0x52018,
3362 .halt_reg = 0x2f044,
3365 .enable_reg = 0x52018,
3375 .halt_reg = 0x2f054,
3378 .enable_reg = 0x52018,
3393 .halt_reg = 0x2f01c,
3395 .hwcg_reg = 0x2f01c,
3398 .enable_reg = 0x52018,
3408 .halt_reg = 0x2f018,
3411 .enable_reg = 0x52018,
3421 .halt_reg = 0x31038,
3424 .enable_reg = 0x52018,
3439 .halt_reg = 0x31034,
3441 .hwcg_reg = 0x31034,
3444 .enable_reg = 0x52018,
3454 .halt_reg = 0x31028,
3456 .hwcg_reg = 0x31028,
3459 .enable_reg = 0x52018,
3469 .halt_reg = 0x31044,
3472 .enable_reg = 0x52018,
3482 .halt_reg = 0x3105c,
3485 .enable_reg = 0x52018,
3500 .halt_reg = 0x31050,
3503 .enable_reg = 0x52018,
3513 .halt_reg = 0x31060,
3516 .enable_reg = 0x52018,
3531 .halt_reg = 0x3101c,
3533 .hwcg_reg = 0x3101c,
3536 .enable_reg = 0x52018,
3546 .halt_reg = 0x31018,
3549 .enable_reg = 0x52018,
3559 .halt_reg = 0x8d038,
3562 .enable_reg = 0x52000,
3577 .halt_reg = 0x8d034,
3579 .hwcg_reg = 0x8d034,
3582 .enable_reg = 0x52000,
3592 .halt_reg = 0x8d028,
3594 .hwcg_reg = 0x8d028,
3597 .enable_reg = 0x52000,
3607 .halt_reg = 0x8d044,
3610 .enable_reg = 0x52000,
3620 .halt_reg = 0x8d05c,
3623 .enable_reg = 0x52000,
3638 .halt_reg = 0x8d050,
3641 .enable_reg = 0x52000,
3651 .halt_reg = 0x8d060,
3654 .enable_reg = 0x52010,
3669 .halt_reg = 0x8d01c,
3671 .hwcg_reg = 0x8d01c,
3674 .enable_reg = 0x52000,
3684 .halt_reg = 0x8d018,
3687 .enable_reg = 0x52000,
3697 .halt_reg = 0xa4008,
3699 .hwcg_reg = 0xa4008,
3702 .enable_reg = 0x52028,
3712 .halt_reg = 0xa4004,
3715 .enable_reg = 0x52028,
3730 .halt_reg = 0x3300c,
3733 .enable_reg = 0x3300c,
3734 .enable_mask = BIT(0),
3748 .halt_reg = 0x33004,
3750 .hwcg_reg = 0x33004,
3753 .enable_reg = 0x33004,
3754 .enable_mask = BIT(0),
3763 .halt_reg = 0x33008,
3766 .enable_reg = 0x33008,
3767 .enable_mask = BIT(0),
3776 .halt_reg = 0x4a018,
3778 .hwcg_reg = 0x4a018,
3781 .enable_reg = 0x4a018,
3782 .enable_mask = BIT(0),
3791 .halt_reg = 0x26008,
3793 .hwcg_reg = 0x26008,
3796 .enable_reg = 0x26008,
3797 .enable_mask = BIT(0),
3806 .halt_reg = 0x2600c,
3808 .hwcg_reg = 0x2600c,
3811 .enable_reg = 0x2600c,
3812 .enable_mask = BIT(0),
3821 .halt_reg = 0x27008,
3823 .hwcg_reg = 0x27008,
3826 .enable_reg = 0x27008,
3827 .enable_mask = BIT(0),
3836 .halt_reg = 0x71008,
3838 .hwcg_reg = 0x71008,
3841 .enable_reg = 0x71008,
3842 .enable_mask = BIT(0),
3851 .halt_reg = 0x32014,
3853 .hwcg_reg = 0x32014,
3856 .enable_reg = 0x32014,
3857 .enable_mask = BIT(0),
3866 .halt_reg = 0x32008,
3868 .hwcg_reg = 0x32008,
3871 .enable_reg = 0x32008,
3872 .enable_mask = BIT(0),
3881 .halt_reg = 0x32010,
3883 .hwcg_reg = 0x32010,
3886 .enable_reg = 0x32010,
3887 .enable_mask = BIT(0),
3896 .halt_reg = 0x3200c,
3898 .hwcg_reg = 0x3200c,
3901 .enable_reg = 0x3200c,
3902 .enable_mask = BIT(0),
3911 .halt_reg = 0x23018,
3914 .enable_reg = 0x52020,
3924 .halt_reg = 0x23008,
3927 .enable_reg = 0x52020,
3937 .halt_reg = 0x42280,
3940 .enable_reg = 0x52028,
3955 .halt_reg = 0x423c0,
3958 .enable_reg = 0x52028,
3973 .halt_reg = 0x42004,
3976 .enable_reg = 0x52020,
3991 .halt_reg = 0x4213c,
3994 .enable_reg = 0x52020,
4009 .halt_reg = 0x42274,
4012 .enable_reg = 0x52020,
4027 .halt_reg = 0x423b4,
4030 .enable_reg = 0x52020,
4045 .halt_reg = 0x424f4,
4048 .enable_reg = 0x52020,
4063 .halt_reg = 0x4262c,
4066 .enable_reg = 0x52020,
4081 .halt_reg = 0x42764,
4084 .enable_reg = 0x52020,
4099 .halt_reg = 0x4289c,
4102 .enable_reg = 0x52020,
4117 .halt_reg = 0x23168,
4120 .enable_reg = 0x52008,
4130 .halt_reg = 0x23158,
4133 .enable_reg = 0x52008,
4143 .halt_reg = 0x18280,
4146 .enable_reg = 0x52028,
4161 .halt_reg = 0x183c0,
4164 .enable_reg = 0x52028,
4179 .halt_reg = 0x18004,
4182 .enable_reg = 0x52008,
4197 .halt_reg = 0x1813c,
4200 .enable_reg = 0x52008,
4215 .halt_reg = 0x18274,
4218 .enable_reg = 0x52008,
4233 .halt_reg = 0x183b4,
4236 .enable_reg = 0x52008,
4251 .halt_reg = 0x184f4,
4254 .enable_reg = 0x52008,
4269 .halt_reg = 0x1862c,
4272 .enable_reg = 0x52008,
4287 .halt_reg = 0x18764,
4290 .enable_reg = 0x52008,
4305 .halt_reg = 0x1889c,
4308 .enable_reg = 0x52010,
4323 .halt_reg = 0x232b8,
4326 .enable_reg = 0x52010,
4336 .halt_reg = 0x232a8,
4339 .enable_reg = 0x52010,
4340 .enable_mask = BIT(0),
4349 .halt_reg = 0x1e280,
4352 .enable_reg = 0x52028,
4367 .halt_reg = 0x1e3c0,
4370 .enable_reg = 0x52028,
4385 .halt_reg = 0x1e004,
4388 .enable_reg = 0x52010,
4403 .halt_reg = 0x1e13c,
4406 .enable_reg = 0x52010,
4421 .halt_reg = 0x1e274,
4424 .enable_reg = 0x52010,
4439 .halt_reg = 0x1e3b4,
4442 .enable_reg = 0x52010,
4457 .halt_reg = 0x1e4f4,
4460 .enable_reg = 0x52010,
4475 .halt_reg = 0x1e62c,
4478 .enable_reg = 0x52010,
4493 .halt_reg = 0x1e764,
4496 .enable_reg = 0x52010,
4511 .halt_reg = 0x1e89c,
4514 .enable_reg = 0x52010,
4529 .halt_reg = 0x23000,
4531 .hwcg_reg = 0x23000,
4534 .enable_reg = 0x52020,
4544 .halt_reg = 0x23004,
4546 .hwcg_reg = 0x23004,
4549 .enable_reg = 0x52020,
4559 .halt_reg = 0x23150,
4561 .hwcg_reg = 0x23150,
4564 .enable_reg = 0x52008,
4574 .halt_reg = 0x23154,
4576 .hwcg_reg = 0x23154,
4579 .enable_reg = 0x52008,
4589 .halt_reg = 0x232a0,
4591 .hwcg_reg = 0x232a0,
4594 .enable_reg = 0x52010,
4604 .halt_reg = 0x232a4,
4606 .hwcg_reg = 0x232a4,
4609 .enable_reg = 0x52010,
4619 .halt_reg = 0x14010,
4622 .enable_reg = 0x14010,
4623 .enable_mask = BIT(0),
4632 .halt_reg = 0x14004,
4635 .enable_reg = 0x14004,
4636 .enable_mask = BIT(0),
4650 .halt_reg = 0x16010,
4653 .enable_reg = 0x16010,
4654 .enable_mask = BIT(0),
4663 .halt_reg = 0x16004,
4666 .enable_reg = 0x16004,
4667 .enable_mask = BIT(0),
4681 .halt_reg = 0x2d014,
4683 .hwcg_reg = 0x2d014,
4686 .enable_reg = 0x2d014,
4687 .enable_mask = BIT(0),
4696 .halt_reg = 0x77024,
4698 .hwcg_reg = 0x77024,
4701 .enable_reg = 0x77024,
4702 .enable_mask = BIT(0),
4711 .halt_reg = 0x77018,
4713 .hwcg_reg = 0x77018,
4716 .enable_reg = 0x77018,
4717 .enable_mask = BIT(0),
4731 .halt_reg = 0x77074,
4733 .hwcg_reg = 0x77074,
4736 .enable_reg = 0x77074,
4737 .enable_mask = BIT(0),
4751 .halt_reg = 0x770b0,
4753 .hwcg_reg = 0x770b0,
4756 .enable_reg = 0x770b0,
4757 .enable_mask = BIT(0),
4771 .halt_reg = 0x7702c,
4774 .enable_reg = 0x7702c,
4775 .enable_mask = BIT(0),
4784 .halt_reg = 0x770cc,
4787 .enable_reg = 0x770cc,
4788 .enable_mask = BIT(0),
4797 .halt_reg = 0x77028,
4800 .enable_reg = 0x77028,
4801 .enable_mask = BIT(0),
4810 .halt_reg = 0x77068,
4812 .hwcg_reg = 0x77068,
4815 .enable_reg = 0x77068,
4816 .enable_mask = BIT(0),
4830 .halt_reg = 0x29018,
4833 .enable_reg = 0x29018,
4834 .enable_mask = BIT(0),
4848 .halt_reg = 0x29028,
4851 .enable_reg = 0x29028,
4852 .enable_mask = BIT(0),
4866 .halt_reg = 0x29024,
4869 .enable_reg = 0x29024,
4870 .enable_mask = BIT(0),
4879 .halt_reg = 0x17018,
4882 .enable_reg = 0x17018,
4883 .enable_mask = BIT(0),
4897 .halt_reg = 0x17028,
4900 .enable_reg = 0x17028,
4901 .enable_mask = BIT(0),
4915 .halt_reg = 0x17024,
4918 .enable_reg = 0x17024,
4919 .enable_mask = BIT(0),
4928 .halt_reg = 0x39018,
4931 .enable_reg = 0x39018,
4932 .enable_mask = BIT(0),
4946 .halt_reg = 0x39028,
4949 .enable_reg = 0x39028,
4950 .enable_mask = BIT(0),
4964 .halt_reg = 0x39024,
4967 .enable_reg = 0x39024,
4968 .enable_mask = BIT(0),
4977 .halt_reg = 0xa1018,
4980 .enable_reg = 0xa1018,
4981 .enable_mask = BIT(0),
4995 .halt_reg = 0xa1028,
4998 .enable_reg = 0xa1028,
4999 .enable_mask = BIT(0),
5013 .halt_reg = 0xa1024,
5016 .enable_reg = 0xa1024,
5017 .enable_mask = BIT(0),
5026 .halt_reg = 0xa2018,
5029 .enable_reg = 0xa2018,
5030 .enable_mask = BIT(0),
5044 .halt_reg = 0xa2028,
5047 .enable_reg = 0xa2028,
5048 .enable_mask = BIT(0),
5062 .halt_reg = 0xa2024,
5065 .enable_reg = 0xa2024,
5066 .enable_mask = BIT(0),
5075 .halt_reg = 0x17288,
5078 .enable_reg = 0x17288,
5079 .enable_mask = BIT(0),
5093 .halt_reg = 0x1728c,
5096 .enable_reg = 0x1728c,
5097 .enable_mask = BIT(0),
5111 .halt_reg = 0x17290,
5114 .enable_reg = 0x17290,
5115 .enable_mask = BIT(0),
5124 .halt_reg = 0x17298,
5127 .enable_reg = 0x17298,
5128 .enable_mask = BIT(0),
5137 .halt_reg = 0x39060,
5140 .enable_reg = 0x39060,
5141 .enable_mask = BIT(0),
5155 .halt_reg = 0x39064,
5158 .enable_reg = 0x39064,
5159 .enable_mask = BIT(0),
5173 .reg = 0x3906c,
5174 .shift = 0,
5188 .halt_reg = 0x39068,
5190 .hwcg_reg = 0x39068,
5193 .enable_reg = 0x39068,
5194 .enable_mask = BIT(0),
5208 .halt_reg = 0xa1060,
5211 .enable_reg = 0xa1060,
5212 .enable_mask = BIT(0),
5226 .halt_reg = 0xa1064,
5229 .enable_reg = 0xa1064,
5230 .enable_mask = BIT(0),
5244 .reg = 0xa106c,
5245 .shift = 0,
5259 .halt_reg = 0xa1068,
5261 .hwcg_reg = 0xa1068,
5264 .enable_reg = 0xa1068,
5265 .enable_mask = BIT(0),
5279 .halt_reg = 0xa2060,
5282 .enable_reg = 0xa2060,
5283 .enable_mask = BIT(0),
5297 .halt_reg = 0xa2064,
5300 .enable_reg = 0xa2064,
5301 .enable_mask = BIT(0),
5315 .reg = 0xa206c,
5316 .shift = 0,
5330 .halt_reg = 0xa2068,
5332 .hwcg_reg = 0xa2068,
5335 .enable_reg = 0xa2068,
5336 .enable_mask = BIT(0),
5350 .halt_reg = 0x9f0a8,
5352 .hwcg_reg = 0x9f0a8,
5355 .enable_reg = 0x9f0a8,
5356 .enable_mask = BIT(0),
5365 .halt_reg = 0x9f060,
5368 .enable_reg = 0x9f060,
5369 .enable_mask = BIT(0),
5378 .halt_reg = 0x9f108,
5381 .enable_reg = 0x9f108,
5382 .enable_mask = BIT(0),
5391 .halt_reg = 0x9f018,
5394 .enable_reg = 0x9f018,
5395 .enable_mask = BIT(0),
5409 .halt_reg = 0x9f0d8,
5412 .enable_reg = 0x9f0d8,
5413 .enable_mask = BIT(0),
5422 .halt_reg = 0x9f048,
5425 .enable_reg = 0x52010,
5435 .halt_reg = 0x9f0b0,
5438 .enable_reg = 0x9f0b0,
5439 .enable_mask = BIT(0),
5448 .halt_reg = 0x9f0c0,
5451 .enable_reg = 0x9f0c0,
5452 .enable_mask = BIT(0),
5461 .halt_reg = 0x9f0a4,
5463 .hwcg_reg = 0x9f0a4,
5466 .enable_reg = 0x9f0a4,
5467 .enable_mask = BIT(0),
5476 .halt_reg = 0x9f044,
5479 .enable_reg = 0x9f044,
5480 .enable_mask = BIT(0),
5494 .halt_reg = 0x9f054,
5497 .enable_reg = 0x9f054,
5498 .enable_mask = BIT(0),
5507 .halt_reg = 0x9f088,
5509 .hwcg_reg = 0x9f088,
5512 .enable_reg = 0x9f088,
5513 .enable_mask = BIT(0),
5527 .halt_reg = 0x2b0a8,
5529 .hwcg_reg = 0x2b0a8,
5532 .enable_reg = 0x2b0a8,
5533 .enable_mask = BIT(0),
5542 .halt_reg = 0x2b060,
5545 .enable_reg = 0x2b060,
5546 .enable_mask = BIT(0),
5555 .halt_reg = 0x2b108,
5558 .enable_reg = 0x2b108,
5559 .enable_mask = BIT(0),
5568 .halt_reg = 0x2b018,
5571 .enable_reg = 0x2b018,
5572 .enable_mask = BIT(0),
5586 .halt_reg = 0x2b0d8,
5589 .enable_reg = 0x2b0d8,
5590 .enable_mask = BIT(0),
5599 .halt_reg = 0x2b048,
5602 .enable_reg = 0x52028,
5603 .enable_mask = BIT(0),
5612 .halt_reg = 0x2b0b0,
5615 .enable_reg = 0x2b0b0,
5616 .enable_mask = BIT(0),
5625 .halt_reg = 0x2b0c0,
5628 .enable_reg = 0x2b0c0,
5629 .enable_mask = BIT(0),
5638 .halt_reg = 0x2b0a4,
5640 .hwcg_reg = 0x2b0a4,
5643 .enable_reg = 0x2b0a4,
5644 .enable_mask = BIT(0),
5653 .halt_reg = 0x2b044,
5656 .enable_reg = 0x2b044,
5657 .enable_mask = BIT(0),
5671 .halt_reg = 0x2b054,
5674 .enable_reg = 0x2b054,
5675 .enable_mask = BIT(0),
5684 .halt_reg = 0x2b088,
5686 .hwcg_reg = 0x2b088,
5689 .enable_reg = 0x2b088,
5690 .enable_mask = BIT(0),
5704 .halt_reg = 0x110a8,
5706 .hwcg_reg = 0x110a8,
5709 .enable_reg = 0x110a8,
5710 .enable_mask = BIT(0),
5719 .halt_reg = 0x11060,
5722 .enable_reg = 0x11060,
5723 .enable_mask = BIT(0),
5732 .halt_reg = 0x11108,
5735 .enable_reg = 0x11108,
5736 .enable_mask = BIT(0),
5745 .halt_reg = 0x11018,
5748 .enable_reg = 0x11018,
5749 .enable_mask = BIT(0),
5763 .halt_reg = 0x110d8,
5766 .enable_reg = 0x110d8,
5767 .enable_mask = BIT(0),
5776 .halt_reg = 0x11048,
5779 .enable_reg = 0x52028,
5789 .halt_reg = 0x110b0,
5792 .enable_reg = 0x110b0,
5793 .enable_mask = BIT(0),
5802 .halt_reg = 0x110c0,
5805 .enable_reg = 0x110c0,
5806 .enable_mask = BIT(0),
5815 .halt_reg = 0x110a4,
5817 .hwcg_reg = 0x110a4,
5820 .enable_reg = 0x110a4,
5821 .enable_mask = BIT(0),
5830 .halt_reg = 0x11044,
5833 .enable_reg = 0x11044,
5834 .enable_mask = BIT(0),
5848 .halt_reg = 0x11054,
5851 .enable_reg = 0x11054,
5852 .enable_mask = BIT(0),
5861 .halt_reg = 0x11088,
5863 .hwcg_reg = 0x11088,
5866 .enable_reg = 0x11088,
5867 .enable_mask = BIT(0),
5881 .halt_reg = 0x32018,
5883 .hwcg_reg = 0x32018,
5886 .enable_reg = 0x32018,
5887 .enable_mask = BIT(0),
5896 .halt_reg = 0x32024,
5898 .hwcg_reg = 0x32024,
5901 .enable_reg = 0x32024,
5902 .enable_mask = BIT(0),
5911 .gdscr = 0xa0004,
5912 .en_rest_wait_val = 0x2,
5913 .en_few_wait_val = 0x2,
5914 .clk_dis_wait_val = 0xf,
5923 .gdscr = 0x2c004,
5924 .en_rest_wait_val = 0x2,
5925 .en_few_wait_val = 0x2,
5926 .clk_dis_wait_val = 0xf,
5935 .gdscr = 0x13004,
5936 .en_rest_wait_val = 0x2,
5937 .en_few_wait_val = 0x2,
5938 .clk_dis_wait_val = 0xf,
5947 .gdscr = 0x58004,
5948 .en_rest_wait_val = 0x2,
5949 .en_few_wait_val = 0x2,
5950 .clk_dis_wait_val = 0xf,
5959 .gdscr = 0x3e000,
5960 .en_rest_wait_val = 0x2,
5961 .en_few_wait_val = 0x2,
5962 .clk_dis_wait_val = 0x2,
5971 .gdscr = 0x6b004,
5972 .en_rest_wait_val = 0x2,
5973 .en_few_wait_val = 0x2,
5974 .clk_dis_wait_val = 0xf,
5983 .gdscr = 0x6c000,
5984 .en_rest_wait_val = 0x2,
5985 .en_few_wait_val = 0x2,
5986 .clk_dis_wait_val = 0x2,
5995 .gdscr = 0x2f004,
5996 .en_rest_wait_val = 0x2,
5997 .en_few_wait_val = 0x2,
5998 .clk_dis_wait_val = 0xf,
6007 .gdscr = 0x30000,
6008 .en_rest_wait_val = 0x2,
6009 .en_few_wait_val = 0x2,
6010 .clk_dis_wait_val = 0x2,
6019 .gdscr = 0x8e000,
6020 .en_rest_wait_val = 0x2,
6021 .en_few_wait_val = 0x2,
6022 .clk_dis_wait_val = 0x2,
6031 .gdscr = 0x31004,
6032 .en_rest_wait_val = 0x2,
6033 .en_few_wait_val = 0x2,
6034 .clk_dis_wait_val = 0xf,
6043 .gdscr = 0x8d004,
6044 .en_rest_wait_val = 0x2,
6045 .en_few_wait_val = 0x2,
6046 .clk_dis_wait_val = 0xf,
6055 .gdscr = 0x9e000,
6056 .en_rest_wait_val = 0x2,
6057 .en_few_wait_val = 0x2,
6058 .clk_dis_wait_val = 0x2,
6067 .gdscr = 0x77004,
6068 .en_rest_wait_val = 0x2,
6069 .en_few_wait_val = 0x2,
6070 .clk_dis_wait_val = 0xf,
6079 .gdscr = 0x29004,
6080 .en_rest_wait_val = 0x2,
6081 .en_few_wait_val = 0x2,
6082 .clk_dis_wait_val = 0xf,
6091 .gdscr = 0x17004,
6092 .en_rest_wait_val = 0x2,
6093 .en_few_wait_val = 0x2,
6094 .clk_dis_wait_val = 0xf,
6103 .gdscr = 0x39004,
6104 .en_rest_wait_val = 0x2,
6105 .en_few_wait_val = 0x2,
6106 .clk_dis_wait_val = 0xf,
6115 .gdscr = 0xa1004,
6116 .en_rest_wait_val = 0x2,
6117 .en_few_wait_val = 0x2,
6118 .clk_dis_wait_val = 0xf,
6127 .gdscr = 0xa2004,
6128 .en_rest_wait_val = 0x2,
6129 .en_few_wait_val = 0x2,
6130 .clk_dis_wait_val = 0xf,
6139 .gdscr = 0x1900c,
6140 .en_rest_wait_val = 0x2,
6141 .en_few_wait_val = 0x2,
6142 .clk_dis_wait_val = 0x2,
6151 .gdscr = 0x5400c,
6152 .en_rest_wait_val = 0x2,
6153 .en_few_wait_val = 0x2,
6154 .clk_dis_wait_val = 0x2,
6163 .gdscr = 0x9f004,
6164 .en_rest_wait_val = 0x2,
6165 .en_few_wait_val = 0x2,
6166 .clk_dis_wait_val = 0xf,
6175 .gdscr = 0x2b004,
6176 .en_rest_wait_val = 0x2,
6177 .en_few_wait_val = 0x2,
6178 .clk_dis_wait_val = 0xf,
6187 .gdscr = 0x11004,
6188 .en_rest_wait_val = 0x2,
6189 .en_few_wait_val = 0x2,
6190 .clk_dis_wait_val = 0xf,
6199 .gdscr = 0x50024,
6200 .en_rest_wait_val = 0x2,
6201 .en_few_wait_val = 0x2,
6202 .clk_dis_wait_val = 0x2,
6211 .gdscr = 0x2a024,
6212 .en_rest_wait_val = 0x2,
6213 .en_few_wait_val = 0x2,
6214 .clk_dis_wait_val = 0x2,
6223 .gdscr = 0xa3024,
6224 .en_rest_wait_val = 0x2,
6225 .en_few_wait_val = 0x2,
6226 .clk_dis_wait_val = 0x2,
6619 [GCC_AV1E_BCR] = { 0x4a000 },
6620 [GCC_CAMERA_BCR] = { 0x26000 },
6621 [GCC_DISPLAY_BCR] = { 0x27000 },
6622 [GCC_GPU_BCR] = { 0x71000 },
6623 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
6624 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
6625 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
6626 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
6627 [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },
6628 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
6629 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
6630 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
6631 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
6632 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },
6633 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },
6634 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },
6635 [GCC_PCIE_2_PHY_BCR] = { 0xa501c },
6636 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },
6637 [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },
6638 [GCC_PCIE_3_BCR] = { 0x58000 },
6639 [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },
6640 [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },
6641 [GCC_PCIE_3_PHY_BCR] = { 0xab01c },
6642 [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },
6643 [GCC_PCIE_4_BCR] = { 0x6b000 },
6644 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },
6645 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },
6646 [GCC_PCIE_4_PHY_BCR] = { 0xb301c },
6647 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },
6648 [GCC_PCIE_5_BCR] = { 0x2f000 },
6649 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },
6650 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },
6651 [GCC_PCIE_5_PHY_BCR] = { 0xaa01c },
6652 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },
6653 [GCC_PCIE_6A_BCR] = { 0x31000 },
6654 [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },
6655 [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },
6656 [GCC_PCIE_6A_PHY_BCR] = { 0xac01c },
6657 [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },
6658 [GCC_PCIE_6B_BCR] = { 0x8d000 },
6659 [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },
6660 [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },
6661 [GCC_PCIE_6B_PHY_BCR] = { 0xb501c },
6662 [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },
6663 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
6664 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
6665 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
6666 [GCC_PCIE_RSCC_BCR] = { 0xa4000 },
6667 [GCC_PDM_BCR] = { 0x33000 },
6668 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },
6669 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
6670 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
6671 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },
6672 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },
6673 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
6674 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
6675 [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },
6676 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },
6677 [GCC_SDCC2_BCR] = { 0x14000 },
6678 [GCC_SDCC4_BCR] = { 0x16000 },
6679 [GCC_UFS_PHY_BCR] = { 0x77000 },
6680 [GCC_USB20_PRIM_BCR] = { 0x29000 },
6681 [GCC_USB30_MP_BCR] = { 0x17000 },
6682 [GCC_USB30_PRIM_BCR] = { 0x39000 },
6683 [GCC_USB30_SEC_BCR] = { 0xa1000 },
6684 [GCC_USB30_TERT_BCR] = { 0xa2000 },
6685 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },
6686 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },
6687 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
6688 [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },
6689 [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },
6690 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
6691 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
6692 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
6693 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
6694 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
6695 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
6696 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
6697 [GCC_USB4_0_BCR] = { 0x9f000 },
6698 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
6699 [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
6700 [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
6701 [GCC_USB4_1_BCR] = { 0x2b000 },
6702 [GCC_USB4_2_BCR] = { 0x11000 },
6703 [GCC_USB_0_PHY_BCR] = { 0x50020 },
6704 [GCC_USB_1_PHY_BCR] = { 0x2a020 },
6705 [GCC_USB_2_PHY_BCR] = { 0xa3020 },
6706 [GCC_VIDEO_BCR] = { 0x32000 },
6740 .max_register = 0x1f41f0,
6775 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ in gcc_x1e80100_probe()
6776 qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ in gcc_x1e80100_probe()
6777 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ in gcc_x1e80100_probe()
6778 qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ in gcc_x1e80100_probe()
6779 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ in gcc_x1e80100_probe()
6780 qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ in gcc_x1e80100_probe()
6781 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_x1e80100_probe()
6784 regmap_write(regmap, 0x52224, 0x0); in gcc_x1e80100_probe()