Lines Matching +full:0 +full:x32000
56 .offset = 0x0,
59 .enable_reg = 0x52018,
60 .enable_mask = BIT(0),
73 { 0x1, 2 },
78 .offset = 0x0,
95 .offset = 0x4000,
98 .enable_reg = 0x52018,
112 .offset = 0x7000,
115 .enable_reg = 0x52018,
129 .offset = 0x9000,
132 .enable_reg = 0x52018,
146 { P_BI_TCXO, 0 },
158 { P_BI_TCXO, 0 },
172 { P_BI_TCXO, 0 },
182 { P_BI_TCXO, 0 },
196 { P_BI_TCXO, 0 },
204 { P_PCIE_1_PHY_AUX_CLK, 0 },
214 { P_BI_TCXO, 0 },
228 { P_BI_TCXO, 0 },
244 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
254 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
264 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
274 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
284 .reg = 0x6b070,
298 .reg = 0x8d094,
299 .shift = 0,
313 .reg = 0x8d078,
327 .reg = 0x77064,
328 .shift = 0,
342 .reg = 0x770e0,
343 .shift = 0,
357 .reg = 0x77054,
358 .shift = 0,
372 .reg = 0x3906c,
373 .shift = 0,
387 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
388 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
389 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
394 .cmd_rcgr = 0x64004,
409 .cmd_rcgr = 0x65004,
424 .cmd_rcgr = 0x66004,
439 F(19200000, P_BI_TCXO, 1, 0, 0),
444 .cmd_rcgr = 0x6b074,
459 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
464 .cmd_rcgr = 0x6b058,
465 .mnd_width = 0,
479 .cmd_rcgr = 0x8d07c,
494 .cmd_rcgr = 0x8d060,
495 .mnd_width = 0,
509 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
514 .cmd_rcgr = 0x33010,
515 .mnd_width = 0,
529 .cmd_rcgr = 0x17008,
530 .mnd_width = 0,
544 .cmd_rcgr = 0x17024,
545 .mnd_width = 0,
559 .cmd_rcgr = 0x17040,
560 .mnd_width = 0,
574 .cmd_rcgr = 0x1705c,
575 .mnd_width = 0,
589 .cmd_rcgr = 0x17078,
590 .mnd_width = 0,
604 .cmd_rcgr = 0x17094,
605 .mnd_width = 0,
619 .cmd_rcgr = 0x170b0,
620 .mnd_width = 0,
634 .cmd_rcgr = 0x170cc,
635 .mnd_width = 0,
649 .cmd_rcgr = 0x170e8,
650 .mnd_width = 0,
664 .cmd_rcgr = 0x17104,
665 .mnd_width = 0,
681 F(19200000, P_BI_TCXO, 1, 0, 0),
687 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
690 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
694 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
707 .cmd_rcgr = 0x18010,
724 .cmd_rcgr = 0x18148,
735 F(19200000, P_BI_TCXO, 1, 0, 0),
741 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
744 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
757 .cmd_rcgr = 0x18280,
774 .cmd_rcgr = 0x183b8,
791 .cmd_rcgr = 0x184f0,
808 .cmd_rcgr = 0x18628,
825 .cmd_rcgr = 0x18760,
842 .cmd_rcgr = 0x18898,
859 .cmd_rcgr = 0x1e010,
876 .cmd_rcgr = 0x1e148,
893 .cmd_rcgr = 0x1e280,
910 .cmd_rcgr = 0x1e3b8,
927 .cmd_rcgr = 0x1e4f0,
944 .cmd_rcgr = 0x1e628,
955 F(19200000, P_BI_TCXO, 1, 0, 0),
961 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
964 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
968 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
982 .cmd_rcgr = 0x1e760,
999 .cmd_rcgr = 0x1e898,
1009 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1010 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
1011 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1012 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1013 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1018 .cmd_rcgr = 0x14018,
1034 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1035 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
1036 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1041 .cmd_rcgr = 0x16018,
1056 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1057 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1058 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1059 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1064 .cmd_rcgr = 0x77030,
1079 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1080 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1081 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1086 .cmd_rcgr = 0x77080,
1087 .mnd_width = 0,
1101 F(9600000, P_BI_TCXO, 2, 0, 0),
1102 F(19200000, P_BI_TCXO, 1, 0, 0),
1107 .cmd_rcgr = 0x770b4,
1108 .mnd_width = 0,
1122 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1123 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1124 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1129 .cmd_rcgr = 0x77098,
1130 .mnd_width = 0,
1144 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1145 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1146 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1147 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1152 .cmd_rcgr = 0x3902c,
1167 .cmd_rcgr = 0x39044,
1168 .mnd_width = 0,
1182 .cmd_rcgr = 0x39070,
1183 .mnd_width = 0,
1197 .reg = 0x3905c,
1198 .shift = 0,
1212 .halt_reg = 0x1003c,
1214 .hwcg_reg = 0x1003c,
1217 .enable_reg = 0x52000,
1227 .halt_reg = 0x770e4,
1229 .hwcg_reg = 0x770e4,
1232 .enable_reg = 0x770e4,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0x770e4,
1249 .hwcg_reg = 0x770e4,
1252 .enable_reg = 0x770e4,
1267 .halt_reg = 0x3908c,
1269 .hwcg_reg = 0x3908c,
1272 .enable_reg = 0x3908c,
1273 .enable_mask = BIT(0),
1287 .halt_reg = 0x38004,
1289 .hwcg_reg = 0x38004,
1292 .enable_reg = 0x52000,
1302 .halt_reg = 0x26010,
1304 .hwcg_reg = 0x26010,
1307 .enable_reg = 0x26010,
1308 .enable_mask = BIT(0),
1317 .halt_reg = 0x2601c,
1319 .hwcg_reg = 0x2601c,
1322 .enable_reg = 0x2601c,
1323 .enable_mask = BIT(0),
1332 .halt_reg = 0x10028,
1334 .hwcg_reg = 0x10028,
1337 .enable_reg = 0x52000,
1347 .halt_reg = 0x39088,
1349 .hwcg_reg = 0x39088,
1352 .enable_reg = 0x39088,
1353 .enable_mask = BIT(0),
1367 .halt_reg = 0x10030,
1369 .hwcg_reg = 0x10030,
1372 .enable_reg = 0x52008,
1382 .halt_reg = 0x71154,
1384 .hwcg_reg = 0x71154,
1387 .enable_reg = 0x71154,
1388 .enable_mask = BIT(0),
1397 .halt_reg = 0x1004c,
1399 .hwcg_reg = 0x1004c,
1402 .enable_reg = 0x52000,
1412 .halt_reg = 0x2700c,
1414 .hwcg_reg = 0x2700c,
1417 .enable_reg = 0x2700c,
1418 .enable_mask = BIT(0),
1427 .halt_reg = 0x64000,
1430 .enable_reg = 0x64000,
1431 .enable_mask = BIT(0),
1445 .halt_reg = 0x65000,
1448 .enable_reg = 0x65000,
1449 .enable_mask = BIT(0),
1463 .halt_reg = 0x66000,
1466 .enable_reg = 0x66000,
1467 .enable_mask = BIT(0),
1483 .enable_reg = 0x52000,
1500 .enable_reg = 0x52000,
1515 .halt_reg = 0x71010,
1517 .hwcg_reg = 0x71010,
1520 .enable_reg = 0x71010,
1521 .enable_mask = BIT(0),
1530 .halt_reg = 0x71018,
1533 .enable_reg = 0x71018,
1534 .enable_mask = BIT(0),
1543 .halt_reg = 0x6b03c,
1546 .enable_reg = 0x52008,
1561 .halt_reg = 0x6b038,
1563 .hwcg_reg = 0x6b038,
1566 .enable_reg = 0x52008,
1576 .halt_reg = 0x6b02c,
1578 .hwcg_reg = 0x6b02c,
1581 .enable_reg = 0x52008,
1591 .halt_reg = 0x6b054,
1594 .enable_reg = 0x52000,
1609 .halt_reg = 0x6b048,
1612 .enable_reg = 0x52008,
1627 .halt_reg = 0x6b020,
1629 .hwcg_reg = 0x6b020,
1632 .enable_reg = 0x52008,
1633 .enable_mask = BIT(0),
1642 .halt_reg = 0x6b01c,
1645 .enable_reg = 0x52008,
1655 .halt_reg = 0x8d038,
1658 .enable_reg = 0x52000,
1673 .halt_reg = 0x8d034,
1675 .hwcg_reg = 0x8d034,
1678 .enable_reg = 0x52000,
1688 .halt_reg = 0x8d028,
1690 .hwcg_reg = 0x8d028,
1693 .enable_reg = 0x52000,
1703 .halt_reg = 0x8d044,
1706 .enable_reg = 0x52000,
1721 .halt_reg = 0x8d05c,
1724 .enable_reg = 0x52000,
1739 .halt_reg = 0x8d050,
1742 .enable_reg = 0x52000,
1757 .halt_reg = 0x8d01c,
1759 .hwcg_reg = 0x8d01c,
1762 .enable_reg = 0x52000,
1772 .halt_reg = 0x8d018,
1775 .enable_reg = 0x52000,
1785 .halt_reg = 0x3300c,
1788 .enable_reg = 0x3300c,
1789 .enable_mask = BIT(0),
1803 .halt_reg = 0x33004,
1805 .hwcg_reg = 0x33004,
1808 .enable_reg = 0x33004,
1809 .enable_mask = BIT(0),
1818 .halt_reg = 0x33008,
1821 .enable_reg = 0x33008,
1822 .enable_mask = BIT(0),
1831 .halt_reg = 0x26008,
1833 .hwcg_reg = 0x26008,
1836 .enable_reg = 0x26008,
1837 .enable_mask = BIT(0),
1846 .halt_reg = 0x2600c,
1848 .hwcg_reg = 0x2600c,
1851 .enable_reg = 0x2600c,
1852 .enable_mask = BIT(0),
1861 .halt_reg = 0x27008,
1863 .hwcg_reg = 0x27008,
1866 .enable_reg = 0x27008,
1867 .enable_mask = BIT(0),
1876 .halt_reg = 0x71008,
1878 .hwcg_reg = 0x71008,
1881 .enable_reg = 0x71008,
1882 .enable_mask = BIT(0),
1891 .halt_reg = 0x6b018,
1893 .hwcg_reg = 0x6b018,
1896 .enable_reg = 0x52000,
1906 .halt_reg = 0x32014,
1908 .hwcg_reg = 0x32014,
1911 .enable_reg = 0x32014,
1912 .enable_mask = BIT(0),
1921 .halt_reg = 0x32008,
1923 .hwcg_reg = 0x32008,
1926 .enable_reg = 0x32008,
1927 .enable_mask = BIT(0),
1936 .halt_reg = 0x32010,
1938 .hwcg_reg = 0x32010,
1941 .enable_reg = 0x32010,
1942 .enable_mask = BIT(0),
1951 .halt_reg = 0x3200c,
1953 .hwcg_reg = 0x3200c,
1956 .enable_reg = 0x3200c,
1957 .enable_mask = BIT(0),
1966 .halt_reg = 0x23144,
1969 .enable_reg = 0x52008,
1979 .halt_reg = 0x17004,
1982 .enable_reg = 0x52008,
1997 .halt_reg = 0x17020,
2000 .enable_reg = 0x52008,
2015 .halt_reg = 0x1703c,
2018 .enable_reg = 0x52008,
2033 .halt_reg = 0x17058,
2036 .enable_reg = 0x52008,
2051 .halt_reg = 0x17074,
2054 .enable_reg = 0x52008,
2069 .halt_reg = 0x17090,
2072 .enable_reg = 0x52008,
2087 .halt_reg = 0x170ac,
2090 .enable_reg = 0x52008,
2105 .halt_reg = 0x170c8,
2108 .enable_reg = 0x52008,
2123 .halt_reg = 0x170e4,
2126 .enable_reg = 0x52010,
2141 .halt_reg = 0x17100,
2144 .enable_reg = 0x52010,
2159 .halt_reg = 0x23140,
2161 .hwcg_reg = 0x23140,
2164 .enable_reg = 0x52008,
2174 .halt_reg = 0x23294,
2177 .enable_reg = 0x52008,
2187 .halt_reg = 0x23284,
2190 .enable_reg = 0x52008,
2200 .halt_reg = 0x18004,
2203 .enable_reg = 0x52008,
2218 .halt_reg = 0x1813c,
2221 .enable_reg = 0x52008,
2236 .halt_reg = 0x18274,
2239 .enable_reg = 0x52008,
2254 .halt_reg = 0x183ac,
2257 .enable_reg = 0x52008,
2272 .halt_reg = 0x184e4,
2275 .enable_reg = 0x52008,
2290 .halt_reg = 0x1861c,
2293 .enable_reg = 0x52008,
2308 .halt_reg = 0x18754,
2311 .enable_reg = 0x52008,
2326 .halt_reg = 0x1888c,
2329 .enable_reg = 0x52010,
2344 .halt_reg = 0x23004,
2347 .enable_reg = 0x52010,
2357 .halt_reg = 0x233d4,
2360 .enable_reg = 0x52010,
2361 .enable_mask = BIT(0),
2370 .halt_reg = 0x1e004,
2373 .enable_reg = 0x52010,
2388 .halt_reg = 0x1e13c,
2391 .enable_reg = 0x52010,
2406 .halt_reg = 0x1e274,
2409 .enable_reg = 0x52010,
2424 .halt_reg = 0x1e3ac,
2427 .enable_reg = 0x52010,
2442 .halt_reg = 0x1e4e4,
2445 .enable_reg = 0x52010,
2460 .halt_reg = 0x1e61c,
2463 .enable_reg = 0x52010,
2478 .halt_reg = 0x1e754,
2481 .enable_reg = 0x52010,
2496 .halt_reg = 0x1e88c,
2499 .enable_reg = 0x52010,
2514 .halt_reg = 0x2327c,
2516 .hwcg_reg = 0x2327c,
2519 .enable_reg = 0x52008,
2529 .halt_reg = 0x23280,
2531 .hwcg_reg = 0x23280,
2534 .enable_reg = 0x52008,
2544 .halt_reg = 0x233cc,
2546 .hwcg_reg = 0x233cc,
2549 .enable_reg = 0x52010,
2559 .halt_reg = 0x233d0,
2561 .hwcg_reg = 0x233d0,
2564 .enable_reg = 0x52010,
2574 .halt_reg = 0x14010,
2577 .enable_reg = 0x14010,
2578 .enable_mask = BIT(0),
2587 .halt_reg = 0x14004,
2590 .enable_reg = 0x14004,
2591 .enable_mask = BIT(0),
2605 .halt_reg = 0x16010,
2608 .enable_reg = 0x16010,
2609 .enable_mask = BIT(0),
2618 .halt_reg = 0x16004,
2621 .enable_reg = 0x16004,
2622 .enable_mask = BIT(0),
2636 .halt_reg = 0x77024,
2638 .hwcg_reg = 0x77024,
2641 .enable_reg = 0x77024,
2642 .enable_mask = BIT(0),
2651 .halt_reg = 0x77018,
2653 .hwcg_reg = 0x77018,
2656 .enable_reg = 0x77018,
2657 .enable_mask = BIT(0),
2671 .halt_reg = 0x77018,
2673 .hwcg_reg = 0x77018,
2676 .enable_reg = 0x77018,
2691 .halt_reg = 0x77074,
2693 .hwcg_reg = 0x77074,
2696 .enable_reg = 0x77074,
2697 .enable_mask = BIT(0),
2711 .halt_reg = 0x77074,
2713 .hwcg_reg = 0x77074,
2716 .enable_reg = 0x77074,
2731 .halt_reg = 0x770b0,
2733 .hwcg_reg = 0x770b0,
2736 .enable_reg = 0x770b0,
2737 .enable_mask = BIT(0),
2751 .halt_reg = 0x770b0,
2753 .hwcg_reg = 0x770b0,
2756 .enable_reg = 0x770b0,
2771 .halt_reg = 0x7702c,
2774 .enable_reg = 0x7702c,
2775 .enable_mask = BIT(0),
2789 .halt_reg = 0x770cc,
2792 .enable_reg = 0x770cc,
2793 .enable_mask = BIT(0),
2807 .halt_reg = 0x77028,
2810 .enable_reg = 0x77028,
2811 .enable_mask = BIT(0),
2825 .halt_reg = 0x77068,
2827 .hwcg_reg = 0x77068,
2830 .enable_reg = 0x77068,
2831 .enable_mask = BIT(0),
2845 .halt_reg = 0x77068,
2847 .hwcg_reg = 0x77068,
2850 .enable_reg = 0x77068,
2865 .halt_reg = 0x39018,
2868 .enable_reg = 0x39018,
2869 .enable_mask = BIT(0),
2883 .halt_reg = 0x39028,
2886 .enable_reg = 0x39028,
2887 .enable_mask = BIT(0),
2901 .halt_reg = 0x39024,
2904 .enable_reg = 0x39024,
2905 .enable_mask = BIT(0),
2914 .halt_reg = 0x39060,
2917 .enable_reg = 0x39060,
2918 .enable_mask = BIT(0),
2932 .halt_reg = 0x39064,
2935 .enable_reg = 0x39064,
2936 .enable_mask = BIT(0),
2950 .halt_reg = 0x39068,
2952 .hwcg_reg = 0x39068,
2955 .enable_reg = 0x39068,
2956 .enable_mask = BIT(0),
2970 .halt_reg = 0x32018,
2972 .hwcg_reg = 0x32018,
2975 .enable_reg = 0x32018,
2976 .enable_mask = BIT(0),
2985 .halt_reg = 0x32024,
2987 .hwcg_reg = 0x32024,
2990 .enable_reg = 0x32024,
2991 .enable_mask = BIT(0),
3000 .gdscr = 0x6b004,
3001 .collapse_ctrl = 0x52020,
3002 .collapse_mask = BIT(0),
3011 .gdscr = 0x6c000,
3012 .collapse_ctrl = 0x52020,
3022 .gdscr = 0x8d004,
3023 .collapse_ctrl = 0x52020,
3033 .gdscr = 0x8e000,
3034 .collapse_ctrl = 0x52020,
3044 .gdscr = 0x77004,
3053 .gdscr = 0x9e000,
3062 .gdscr = 0x39004,
3071 .gdscr = 0x50018,
3246 [GCC_CAMERA_BCR] = { 0x26000 },
3247 [GCC_DISPLAY_BCR] = { 0x27000 },
3248 [GCC_GPU_BCR] = { 0x71000 },
3249 [GCC_PCIE_0_BCR] = { 0x6b000 },
3250 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3251 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3252 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3253 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3254 [GCC_PCIE_1_BCR] = { 0x8d000 },
3255 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3256 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3257 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3258 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
3259 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3260 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3261 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3262 [GCC_PDM_BCR] = { 0x33000 },
3263 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3264 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3265 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },
3266 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3267 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3268 [GCC_SDCC2_BCR] = { 0x14000 },
3269 [GCC_SDCC4_BCR] = { 0x16000 },
3270 [GCC_UFS_PHY_BCR] = { 0x77000 },
3271 [GCC_USB30_PRIM_BCR] = { 0x39000 },
3272 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3273 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3274 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3275 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3276 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3277 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3278 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3279 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
3280 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
3281 [GCC_VIDEO_BCR] = { 0x32000 },
3318 .max_register = 0x1f41f0,
3356 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ in gcc_sm8550_probe()
3357 qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ in gcc_sm8550_probe()
3358 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ in gcc_sm8550_probe()
3359 qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ in gcc_sm8550_probe()
3360 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sm8550_probe()
3361 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ in gcc_sm8550_probe()
3362 qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ in gcc_sm8550_probe()
3365 regmap_write(regmap, 0x52024, 0x0); in gcc_sm8550_probe()