Lines Matching +full:0 +full:x3800c
42 .offset = 0x0,
45 .enable_reg = 0x79000,
46 .enable_mask = BIT(0),
85 .offset = 0x3000,
88 .enable_reg = 0x79000,
102 .offset = 0x4000,
105 .enable_reg = 0x79000,
119 .offset = 0x5000,
122 .enable_reg = 0x79000,
136 .offset = 0x6000,
139 .enable_reg = 0x79000,
166 .offset = 0x7000,
169 .enable_reg = 0x79000,
196 .offset = 0x8000,
199 .enable_reg = 0x79000,
226 .offset = 0x9000,
229 .enable_reg = 0x79000,
256 { P_BI_TCXO, 0 },
268 { P_BI_TCXO, 0 },
282 { P_BI_TCXO, 0 },
296 { P_BI_TCXO, 0 },
310 { P_BI_TCXO, 0 },
322 { P_BI_TCXO, 0 },
332 { P_BI_TCXO, 0 },
344 { P_BI_TCXO, 0 },
356 { P_BI_TCXO, 0 },
376 { P_BI_TCXO, 0 },
388 { P_BI_TCXO, 0 },
406 { P_BI_TCXO, 0 },
420 { P_BI_TCXO, 0 },
434 { P_BI_TCXO, 0 },
450 { P_BI_TCXO, 0 },
460 F(19200000, P_BI_TCXO, 1, 0, 0),
461 F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0),
462 F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0),
467 .cmd_rcgr = 0x56088,
468 .mnd_width = 0,
481 F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0),
482 F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
483 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
488 .cmd_rcgr = 0x52004,
502 F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
503 F(240000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
504 F(320000000, P_GPLL8_OUT_MAIN, 1.5, 0, 0),
505 F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
506 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
511 .cmd_rcgr = 0x560c8,
512 .mnd_width = 0,
525 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
526 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
527 F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0),
528 F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
529 F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0),
534 .cmd_rcgr = 0x55030,
535 .mnd_width = 0,
548 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
549 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
550 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
555 .cmd_rcgr = 0x53004,
556 .mnd_width = 0,
569 .cmd_rcgr = 0x5506c,
570 .mnd_width = 0,
583 .cmd_rcgr = 0x53024,
584 .mnd_width = 0,
597 .cmd_rcgr = 0x550a4,
598 .mnd_width = 0,
611 .cmd_rcgr = 0x53044,
612 .mnd_width = 0,
625 .cmd_rcgr = 0x550e0,
626 .mnd_width = 0,
639 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
640 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
641 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
642 F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
647 .cmd_rcgr = 0x55000,
648 .mnd_width = 0,
661 F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
662 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
663 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
668 .cmd_rcgr = 0x50000,
682 .cmd_rcgr = 0x5001c,
696 F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0),
697 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
698 F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0),
699 F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
700 F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0),
705 .cmd_rcgr = 0x52028,
706 .mnd_width = 0,
719 F(19200000, P_BI_TCXO, 1, 0, 0),
726 .cmd_rcgr = 0x51000,
740 .cmd_rcgr = 0x5101c,
754 .cmd_rcgr = 0x51038,
768 .cmd_rcgr = 0x51054,
782 F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
783 F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0),
784 F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
785 F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
786 F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0),
787 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
792 .cmd_rcgr = 0x54010,
793 .mnd_width = 0,
806 .cmd_rcgr = 0x54048,
807 .mnd_width = 0,
820 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
821 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
822 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
823 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
828 .cmd_rcgr = 0x4d004,
842 .cmd_rcgr = 0x4e004,
856 .cmd_rcgr = 0x4f004,
870 F(19200000, P_BI_TCXO, 1, 0, 0),
871 F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
876 .cmd_rcgr = 0x20010,
877 .mnd_width = 0,
892 F(19200000, P_BI_TCXO, 1, 0, 0),
897 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
900 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
904 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
905 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
917 .cmd_rcgr = 0x1f148,
933 .cmd_rcgr = 0x1f278,
949 .cmd_rcgr = 0x1f3a8,
965 .cmd_rcgr = 0x1f4d8,
981 .cmd_rcgr = 0x1f608,
997 .cmd_rcgr = 0x1f738,
1013 .cmd_rcgr = 0x39148,
1029 .cmd_rcgr = 0x39278,
1045 .cmd_rcgr = 0x393a8,
1061 .cmd_rcgr = 0x394d8,
1077 .cmd_rcgr = 0x39608,
1093 .cmd_rcgr = 0x39738,
1106 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1107 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1108 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1109 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1114 .cmd_rcgr = 0x38028,
1128 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1129 F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1130 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1131 F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
1136 .cmd_rcgr = 0x38010,
1137 .mnd_width = 0,
1151 F(19200000, P_BI_TCXO, 1, 0, 0),
1152 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1153 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1154 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1159 .cmd_rcgr = 0x1e00c,
1173 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1174 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1175 F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
1176 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1177 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1182 .cmd_rcgr = 0x45020,
1196 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1197 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1198 F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1199 F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
1204 .cmd_rcgr = 0x45048,
1205 .mnd_width = 0,
1218 F(9600000, P_BI_TCXO, 2, 0, 0),
1219 F(19200000, P_BI_TCXO, 1, 0, 0),
1224 .cmd_rcgr = 0x4507c,
1225 .mnd_width = 0,
1238 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1239 F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0),
1240 F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1245 .cmd_rcgr = 0x45060,
1246 .mnd_width = 0,
1259 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1260 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1261 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1262 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1267 .cmd_rcgr = 0x1a01c,
1281 F(19200000, P_BI_TCXO, 1, 0, 0),
1282 F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0),
1283 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1284 F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
1289 .cmd_rcgr = 0x1a034,
1290 .mnd_width = 0,
1303 F(19200000, P_BI_TCXO, 1, 0, 0),
1308 .cmd_rcgr = 0x1a060,
1309 .mnd_width = 0,
1322 .cmd_rcgr = 0x42030,
1323 .mnd_width = 0,
1336 F(19200000, P_BI_TCXO, 1, 0, 0),
1337 F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0),
1338 F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0),
1343 .cmd_rcgr = 0x42018,
1344 .mnd_width = 0,
1357 .halt_reg = 0x1d004,
1359 .hwcg_reg = 0x1d004,
1362 .enable_reg = 0x1d004,
1363 .enable_mask = BIT(0),
1372 .halt_reg = 0x1d008,
1374 .hwcg_reg = 0x1d008,
1377 .enable_reg = 0x1d008,
1378 .enable_mask = BIT(0),
1387 .halt_reg = 0x4204c,
1390 .enable_reg = 0x4204c,
1391 .enable_mask = BIT(0),
1405 .halt_reg = 0x71154,
1408 .enable_reg = 0x71154,
1409 .enable_mask = BIT(0),
1418 .halt_reg = 0x23004,
1420 .hwcg_reg = 0x23004,
1423 .enable_reg = 0x79004,
1433 .halt_reg = 0x17008,
1435 .hwcg_reg = 0x17008,
1438 .enable_reg = 0x17008,
1439 .enable_mask = BIT(0),
1449 .halt_reg = 0x17028,
1452 .enable_reg = 0x17028,
1453 .enable_mask = BIT(0),
1463 .halt_reg = 0x52020,
1466 .enable_reg = 0x52020,
1467 .enable_mask = BIT(0),
1481 .halt_reg = 0x5201c,
1484 .enable_reg = 0x5201c,
1485 .enable_mask = BIT(0),
1499 .halt_reg = 0x5504c,
1502 .enable_reg = 0x5504c,
1503 .enable_mask = BIT(0),
1517 .halt_reg = 0x55088,
1520 .enable_reg = 0x55088,
1521 .enable_mask = BIT(0),
1535 .halt_reg = 0x550c0,
1538 .enable_reg = 0x550c0,
1539 .enable_mask = BIT(0),
1553 .halt_reg = 0x550fc,
1556 .enable_reg = 0x550fc,
1557 .enable_mask = BIT(0),
1571 .halt_reg = 0x560e8,
1574 .enable_reg = 0x560e8,
1575 .enable_mask = BIT(0),
1589 .halt_reg = 0x560f4,
1592 .enable_reg = 0x560f4,
1593 .enable_mask = BIT(0),
1602 .halt_reg = 0x560e0,
1605 .enable_reg = 0x560e0,
1606 .enable_mask = BIT(0),
1620 .halt_reg = 0x560f0,
1623 .enable_reg = 0x560f0,
1624 .enable_mask = BIT(0),
1638 .halt_reg = 0x55050,
1641 .enable_reg = 0x55050,
1642 .enable_mask = BIT(0),
1656 .halt_reg = 0x55048,
1659 .enable_reg = 0x55048,
1660 .enable_mask = BIT(0),
1674 .halt_reg = 0x5301c,
1677 .enable_reg = 0x5301c,
1678 .enable_mask = BIT(0),
1692 .halt_reg = 0x55060,
1695 .enable_reg = 0x55060,
1696 .enable_mask = BIT(0),
1710 .halt_reg = 0x55058,
1713 .enable_reg = 0x55058,
1714 .enable_mask = BIT(0),
1728 .halt_reg = 0x5508c,
1731 .enable_reg = 0x5508c,
1732 .enable_mask = BIT(0),
1746 .halt_reg = 0x55084,
1749 .enable_reg = 0x55084,
1750 .enable_mask = BIT(0),
1764 .halt_reg = 0x5303c,
1767 .enable_reg = 0x5303c,
1768 .enable_mask = BIT(0),
1782 .halt_reg = 0x5509c,
1785 .enable_reg = 0x5509c,
1786 .enable_mask = BIT(0),
1800 .halt_reg = 0x55094,
1803 .enable_reg = 0x55094,
1804 .enable_mask = BIT(0),
1818 .halt_reg = 0x550c4,
1821 .enable_reg = 0x550c4,
1822 .enable_mask = BIT(0),
1836 .halt_reg = 0x550bc,
1839 .enable_reg = 0x550bc,
1840 .enable_mask = BIT(0),
1854 .halt_reg = 0x5305c,
1857 .enable_reg = 0x5305c,
1858 .enable_mask = BIT(0),
1872 .halt_reg = 0x550d4,
1875 .enable_reg = 0x550d4,
1876 .enable_mask = BIT(0),
1890 .halt_reg = 0x550cc,
1893 .enable_reg = 0x550cc,
1894 .enable_mask = BIT(0),
1908 .halt_reg = 0x55100,
1911 .enable_reg = 0x55100,
1912 .enable_mask = BIT(0),
1926 .halt_reg = 0x550f8,
1929 .enable_reg = 0x550f8,
1930 .enable_mask = BIT(0),
1944 .halt_reg = 0x55110,
1947 .enable_reg = 0x55110,
1948 .enable_mask = BIT(0),
1962 .halt_reg = 0x55108,
1965 .enable_reg = 0x55108,
1966 .enable_mask = BIT(0),
1980 .halt_reg = 0x54074,
1983 .enable_reg = 0x54074,
1984 .enable_mask = BIT(0),
1998 .halt_reg = 0x54080,
2001 .enable_reg = 0x54080,
2002 .enable_mask = BIT(0),
2016 .halt_reg = 0x55018,
2019 .enable_reg = 0x55018,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x5501c,
2037 .enable_reg = 0x5501c,
2038 .enable_mask = BIT(0),
2052 .halt_reg = 0x55020,
2055 .enable_reg = 0x55020,
2056 .enable_mask = BIT(0),
2070 .halt_reg = 0x50018,
2073 .enable_reg = 0x50018,
2074 .enable_mask = BIT(0),
2088 .halt_reg = 0x50034,
2091 .enable_reg = 0x50034,
2092 .enable_mask = BIT(0),
2106 .halt_reg = 0x540a4,
2109 .enable_reg = 0x540a4,
2110 .enable_mask = BIT(0),
2124 .halt_reg = 0x52048,
2127 .enable_reg = 0x52048,
2128 .enable_mask = BIT(0),
2142 .halt_reg = 0x5204c,
2145 .enable_reg = 0x5204c,
2146 .enable_mask = BIT(0),
2155 .halt_reg = 0x52040,
2158 .enable_reg = 0x52040,
2159 .enable_mask = BIT(0),
2173 .halt_reg = 0x51018,
2176 .enable_reg = 0x51018,
2177 .enable_mask = BIT(0),
2191 .halt_reg = 0x51034,
2194 .enable_reg = 0x51034,
2195 .enable_mask = BIT(0),
2209 .halt_reg = 0x51050,
2212 .enable_reg = 0x51050,
2213 .enable_mask = BIT(0),
2227 .halt_reg = 0x5106c,
2230 .enable_reg = 0x5106c,
2231 .enable_mask = BIT(0),
2245 .halt_reg = 0x560b0,
2248 .enable_reg = 0x560b0,
2249 .enable_mask = BIT(0),
2263 .halt_reg = 0x560a4,
2266 .enable_reg = 0x79004,
2276 .halt_reg = 0x560a8,
2279 .enable_reg = 0x79004,
2289 .halt_reg = 0x560a0,
2292 .enable_reg = 0x560a0,
2293 .enable_mask = BIT(0),
2307 .halt_reg = 0x54034,
2310 .enable_reg = 0x54034,
2311 .enable_mask = BIT(0),
2325 .halt_reg = 0x54028,
2328 .enable_reg = 0x54028,
2329 .enable_mask = BIT(0),
2343 .halt_reg = 0x54030,
2346 .enable_reg = 0x54030,
2347 .enable_mask = BIT(0),
2361 .halt_reg = 0x5406c,
2364 .enable_reg = 0x5406c,
2365 .enable_mask = BIT(0),
2379 .halt_reg = 0x54060,
2382 .enable_reg = 0x54060,
2383 .enable_mask = BIT(0),
2397 .halt_reg = 0x54068,
2400 .enable_reg = 0x54068,
2401 .enable_mask = BIT(0),
2415 .halt_reg = 0x5409c,
2418 .enable_reg = 0x5409c,
2419 .enable_mask = BIT(0),
2428 .halt_reg = 0x5408c,
2431 .enable_reg = 0x5408c,
2432 .enable_mask = BIT(0),
2446 .halt_reg = 0x54090,
2449 .enable_reg = 0x54090,
2450 .enable_mask = BIT(0),
2459 .halt_reg = 0x2700c,
2461 .hwcg_reg = 0x2700c,
2464 .enable_reg = 0x79004,
2474 .halt_reg = 0x27008,
2477 .enable_reg = 0x79004,
2487 .halt_reg = 0x27004,
2490 .enable_reg = 0x79004,
2500 .halt_reg = 0x1a084,
2503 .enable_reg = 0x1a084,
2504 .enable_mask = BIT(0),
2518 .halt_reg = 0x2b004,
2520 .hwcg_reg = 0x2b004,
2523 .enable_reg = 0x79004,
2534 .halt_reg = 0x1700c,
2536 .hwcg_reg = 0x1700c,
2539 .enable_reg = 0x1700c,
2540 .enable_mask = BIT(0),
2552 .enable_reg = 0x79004,
2566 .halt_reg = 0x17020,
2569 .enable_reg = 0x17020,
2570 .enable_mask = BIT(0),
2579 .halt_reg = 0x17064,
2582 .enable_reg = 0x7900c,
2592 .halt_reg = 0x1702c,
2595 .enable_reg = 0x1702c,
2596 .enable_mask = BIT(0),
2606 .halt_reg = 0x4d000,
2609 .enable_reg = 0x4d000,
2610 .enable_mask = BIT(0),
2624 .halt_reg = 0x4e000,
2627 .enable_reg = 0x4e000,
2628 .enable_mask = BIT(0),
2642 .halt_reg = 0x4f000,
2645 .enable_reg = 0x4f000,
2646 .enable_mask = BIT(0),
2660 .halt_reg = 0x36004,
2662 .hwcg_reg = 0x36004,
2665 .enable_reg = 0x36004,
2666 .enable_mask = BIT(0),
2678 .enable_reg = 0x79004,
2694 .enable_reg = 0x79004,
2708 .halt_reg = 0x3600c,
2711 .enable_reg = 0x3600c,
2712 .enable_mask = BIT(0),
2721 .halt_reg = 0x36018,
2724 .enable_reg = 0x36018,
2725 .enable_mask = BIT(0),
2734 .halt_reg = 0x36048,
2737 .enable_reg = 0x79004,
2747 .halt_reg = 0x36044,
2750 .enable_reg = 0x36044,
2751 .enable_mask = BIT(0),
2760 .halt_reg = 0x42048,
2763 .enable_reg = 0x42048,
2764 .enable_mask = BIT(0),
2778 .halt_reg = 0x2000c,
2781 .enable_reg = 0x2000c,
2782 .enable_mask = BIT(0),
2796 .halt_reg = 0x20004,
2798 .hwcg_reg = 0x20004,
2801 .enable_reg = 0x20004,
2802 .enable_mask = BIT(0),
2811 .halt_reg = 0x20008,
2814 .enable_reg = 0x20008,
2815 .enable_mask = BIT(0),
2824 .halt_reg = 0x21004,
2826 .hwcg_reg = 0x21004,
2829 .enable_reg = 0x79004,
2839 .halt_reg = 0x17014,
2841 .hwcg_reg = 0x17014,
2844 .enable_reg = 0x7900c,
2845 .enable_mask = BIT(0),
2854 .halt_reg = 0x17060,
2856 .hwcg_reg = 0x17060,
2859 .enable_reg = 0x7900c,
2869 .halt_reg = 0x17018,
2871 .hwcg_reg = 0x17018,
2874 .enable_reg = 0x7900c,
2884 .halt_reg = 0x36040,
2886 .hwcg_reg = 0x36040,
2889 .enable_reg = 0x7900c,
2899 .halt_reg = 0x17010,
2901 .hwcg_reg = 0x17010,
2904 .enable_reg = 0x79004,
2914 .halt_reg = 0x1f014,
2917 .enable_reg = 0x7900c,
2927 .halt_reg = 0x1f00c,
2930 .enable_reg = 0x7900c,
2940 .halt_reg = 0x1f144,
2943 .enable_reg = 0x7900c,
2958 .halt_reg = 0x1f274,
2961 .enable_reg = 0x7900c,
2976 .halt_reg = 0x1f3a4,
2979 .enable_reg = 0x7900c,
2994 .halt_reg = 0x1f4d4,
2997 .enable_reg = 0x7900c,
3012 .halt_reg = 0x1f604,
3015 .enable_reg = 0x7900c,
3030 .halt_reg = 0x1f734,
3033 .enable_reg = 0x7900c,
3048 .halt_reg = 0x39014,
3051 .enable_reg = 0x7900c,
3061 .halt_reg = 0x3900c,
3064 .enable_reg = 0x7900c,
3074 .halt_reg = 0x39144,
3077 .enable_reg = 0x7900c,
3092 .halt_reg = 0x39274,
3095 .enable_reg = 0x7900c,
3110 .halt_reg = 0x393a4,
3113 .enable_reg = 0x7900c,
3128 .halt_reg = 0x394d4,
3131 .enable_reg = 0x7900c,
3146 .halt_reg = 0x39604,
3149 .enable_reg = 0x7900c,
3164 .halt_reg = 0x39734,
3167 .enable_reg = 0x7900c,
3182 .halt_reg = 0x1f004,
3185 .enable_reg = 0x7900c,
3195 .halt_reg = 0x1f008,
3197 .hwcg_reg = 0x1f008,
3200 .enable_reg = 0x7900c,
3210 .halt_reg = 0x39004,
3213 .enable_reg = 0x7900c,
3223 .halt_reg = 0x39008,
3225 .hwcg_reg = 0x39008,
3228 .enable_reg = 0x7900c,
3238 .halt_reg = 0x38008,
3241 .enable_reg = 0x38008,
3242 .enable_mask = BIT(0),
3251 .halt_reg = 0x38004,
3254 .enable_reg = 0x38004,
3255 .enable_mask = BIT(0),
3269 .halt_reg = 0x3800c,
3272 .enable_reg = 0x3800c,
3273 .enable_mask = BIT(0),
3287 .halt_reg = 0x1e008,
3290 .enable_reg = 0x1e008,
3291 .enable_mask = BIT(0),
3300 .halt_reg = 0x1e004,
3303 .enable_reg = 0x1e004,
3304 .enable_mask = BIT(0),
3318 .halt_reg = 0x1050c,
3321 .enable_reg = 0x1050c,
3322 .enable_mask = BIT(0),
3332 .halt_reg = 0x2b06c,
3335 .enable_reg = 0x79004,
3336 .enable_mask = BIT(0),
3346 .halt_reg = 0x45098,
3349 .enable_reg = 0x45098,
3350 .enable_mask = BIT(0),
3364 .halt_reg = 0x1a080,
3367 .enable_reg = 0x1a080,
3368 .enable_mask = BIT(0),
3382 .halt_reg = 0x8c000,
3385 .enable_reg = 0x8c000,
3386 .enable_mask = BIT(0),
3395 .halt_reg = 0x45014,
3397 .hwcg_reg = 0x45014,
3400 .enable_reg = 0x45014,
3401 .enable_mask = BIT(0),
3410 .halt_reg = 0x45010,
3412 .hwcg_reg = 0x45010,
3415 .enable_reg = 0x45010,
3416 .enable_mask = BIT(0),
3430 .halt_reg = 0x45044,
3432 .hwcg_reg = 0x45044,
3435 .enable_reg = 0x45044,
3436 .enable_mask = BIT(0),
3450 .halt_reg = 0x45078,
3452 .hwcg_reg = 0x45078,
3455 .enable_reg = 0x45078,
3456 .enable_mask = BIT(0),
3470 .halt_reg = 0x4501c,
3473 .enable_reg = 0x4501c,
3474 .enable_mask = BIT(0),
3483 .halt_reg = 0x45018,
3486 .enable_reg = 0x45018,
3487 .enable_mask = BIT(0),
3496 .halt_reg = 0x45040,
3498 .hwcg_reg = 0x45040,
3501 .enable_reg = 0x45040,
3502 .enable_mask = BIT(0),
3516 .halt_reg = 0x1a010,
3519 .enable_reg = 0x1a010,
3520 .enable_mask = BIT(0),
3534 .halt_reg = 0x1a018,
3537 .enable_reg = 0x1a018,
3538 .enable_mask = BIT(0),
3552 .halt_reg = 0x1a014,
3555 .enable_reg = 0x1a014,
3556 .enable_mask = BIT(0),
3565 .halt_reg = 0x80278,
3568 .enable_reg = 0x80278,
3569 .enable_mask = BIT(0),
3578 .halt_reg = 0x1a054,
3581 .enable_reg = 0x1a054,
3582 .enable_mask = BIT(0),
3598 .enable_reg = 0x1a058,
3599 .enable_mask = BIT(0),
3608 .halt_reg = 0x4200c,
3611 .enable_reg = 0x4200c,
3612 .enable_mask = BIT(0),
3626 .halt_reg = 0x42004,
3629 .enable_reg = 0x42004,
3630 .enable_mask = BIT(0),
3644 .halt_reg = 0x42008,
3647 .enable_reg = 0x42008,
3648 .enable_mask = BIT(0),
3662 .halt_reg = 0x17004,
3664 .hwcg_reg = 0x17004,
3667 .enable_reg = 0x17004,
3668 .enable_mask = BIT(0),
3678 .halt_reg = 0x1701c,
3681 .enable_reg = 0x1701c,
3682 .enable_mask = BIT(0),
3691 .halt_reg = 0x17068,
3694 .enable_reg = 0x79004,
3704 .halt_reg = 0x17024,
3707 .enable_reg = 0x17024,
3708 .enable_mask = BIT(0),
3718 .halt_reg = 0x42014,
3720 .hwcg_reg = 0x42014,
3723 .enable_reg = 0x42014,
3724 .enable_mask = BIT(0),
3733 .halt_reg = 0x42010,
3736 .enable_reg = 0x42010,
3737 .enable_mask = BIT(0),
3751 .halt_reg = 0x42050,
3754 .enable_reg = 0x42050,
3755 .enable_mask = BIT(0),
3769 .gdscr = 0x1a004,
3777 .gdscr = 0x45004,
3785 .gdscr = 0x54004,
3793 .gdscr = 0x5403c,
3801 .gdscr = 0x5607c,
3809 .gdscr = 0x560bc,
3817 .gdscr = 0x7d060,
3826 .gdscr = 0x80074,
3835 .gdscr = 0x80084,
3845 .gdscr = 0x80094,
4084 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
4085 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
4086 [GCC_UFS_PHY_BCR] = { 0x45000 },
4087 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
4088 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
4089 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
4090 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
4091 [GCC_CAMSS_MICRO_BCR] = { 0x560ac },
4113 .max_register = 0xc7000,
4148 regmap_update_bits(regmap, 0x80258, 0x1, 0x1); in gcc_sm6125_probe()
4154 regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000); in gcc_sm6125_probe()
4155 regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000); in gcc_sm6125_probe()
4156 regmap_update_bits(regmap, 0x5103c, 0x3000, 0x2000); in gcc_sm6125_probe()
4157 regmap_update_bits(regmap, 0x51058, 0x3000, 0x2000); in gcc_sm6125_probe()