Lines Matching +full:0 +full:x29000
67 .offset = 0x0,
70 .enable_reg = 0x7d000,
71 .enable_mask = BIT(0),
84 { 0x1, 2 },
89 .offset = 0x0,
106 .offset = 0x4000,
109 .enable_reg = 0x7d000,
123 .offset = 0x5000,
126 .enable_reg = 0x7d000,
140 .offset = 0x6000,
143 .enable_reg = 0x7d000,
157 .offset = 0x8000,
160 .enable_reg = 0x7d000,
174 { P_BI_TCXO, 0 },
186 { P_BI_TCXO, 0 },
202 { P_BI_TCXO, 0 },
216 { P_BI_TCXO, 0 },
226 { P_BI_TCXO, 0 },
238 { P_EMAC0_SGMIIPHY_RCLK, 0 },
248 { P_EMAC0_SGMIIPHY_TCLK, 0 },
258 { P_EMAC0_SGMIIPHY_MAC_RCLK, 0 },
268 { P_EMAC0_SGMIIPHY_MAC_TCLK, 0 },
278 { P_EMAC1_SGMIIPHY_RCLK, 0 },
288 { P_EMAC1_SGMIIPHY_TCLK, 0 },
298 { P_EMAC1_SGMIIPHY_MAC_RCLK, 0 },
308 { P_EMAC1_SGMIIPHY_MAC_TCLK, 0 },
318 { P_PCIE20_PHY_AUX_CLK, 0 },
328 { P_BI_TCXO, 0 },
342 { P_BI_TCXO, 0 },
356 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
366 .reg = 0x71060,
367 .shift = 0,
381 .reg = 0x71058,
382 .shift = 0,
396 .reg = 0x71098,
397 .shift = 0,
411 .reg = 0x71094,
412 .shift = 0,
426 .reg = 0x72060,
427 .shift = 0,
441 .reg = 0x72058,
442 .shift = 0,
456 .reg = 0x72098,
457 .shift = 0,
471 .reg = 0x72094,
472 .shift = 0,
486 .reg = 0x67084,
500 .reg = 0x68050,
514 .reg = 0x53074,
515 .shift = 0,
529 .reg = 0x53058,
543 .reg = 0x27070,
544 .shift = 0,
558 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
563 .cmd_rcgr = 0x710b0,
577 .cmd_rcgr = 0x720b0,
591 F(19200000, P_BI_TCXO, 1, 0, 0),
596 .cmd_rcgr = 0x7102c,
597 .mnd_width = 0,
610 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
611 F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
612 F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),
617 .cmd_rcgr = 0x7107c,
632 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
633 F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
634 F(250000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
639 .cmd_rcgr = 0x71064,
653 .cmd_rcgr = 0x7202c,
654 .mnd_width = 0,
667 .cmd_rcgr = 0x7207c,
681 .cmd_rcgr = 0x72064,
695 F(19200000, P_BI_TCXO, 1, 0, 0),
696 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
697 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
698 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
703 .cmd_rcgr = 0x47004,
717 .cmd_rcgr = 0x48004,
731 .cmd_rcgr = 0x49004,
745 .cmd_rcgr = 0x67044,
759 F(19200000, P_BI_TCXO, 1, 0, 0),
760 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
765 .cmd_rcgr = 0x6706c,
766 .mnd_width = 0,
779 .cmd_rcgr = 0x68064,
793 .cmd_rcgr = 0x68038,
794 .mnd_width = 0,
807 .cmd_rcgr = 0x5305c,
821 .cmd_rcgr = 0x53078,
822 .mnd_width = 0,
835 F(19200000, P_BI_TCXO, 1, 0, 0),
836 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
841 .cmd_rcgr = 0x34010,
842 .mnd_width = 0,
857 F(19200000, P_BI_TCXO, 1, 0, 0),
862 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
865 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
877 .cmd_rcgr = 0x6c010,
893 .cmd_rcgr = 0x6c148,
909 .cmd_rcgr = 0x6c280,
925 .cmd_rcgr = 0x6c3b8,
941 .cmd_rcgr = 0x6c4f0,
957 .cmd_rcgr = 0x6c628,
973 .cmd_rcgr = 0x6c760,
989 .cmd_rcgr = 0x6c898,
1005 .cmd_rcgr = 0x6c9d0,
1016 F(19200000, P_BI_TCXO, 1, 0, 0),
1018 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1019 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1020 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1021 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1022 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1027 .cmd_rcgr = 0x6b014,
1042 F(19200000, P_BI_TCXO, 1, 0, 0),
1043 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1044 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1045 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
1046 F(202000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
1051 .cmd_rcgr = 0x6a018,
1065 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
1070 .cmd_rcgr = 0x27034,
1084 .cmd_rcgr = 0x2704c,
1085 .mnd_width = 0,
1099 F(19200000, P_BI_TCXO, 1, 0, 0),
1104 .cmd_rcgr = 0x27074,
1118 .reg = 0x67088,
1119 .shift = 0,
1133 .reg = 0x68088,
1134 .shift = 0,
1148 .reg = 0x27064,
1149 .shift = 0,
1163 .halt_reg = 0x37004,
1165 .hwcg_reg = 0x37004,
1168 .enable_reg = 0x7d008,
1178 .halt_reg = 0x710ac,
1181 .enable_reg = 0x710ac,
1182 .enable_mask = BIT(0),
1196 .halt_reg = 0x720ac,
1199 .enable_reg = 0x720ac,
1200 .enable_mask = BIT(0),
1214 .halt_reg = 0x71018,
1216 .hwcg_reg = 0x71018,
1219 .enable_reg = 0x71018,
1220 .enable_mask = BIT(0),
1229 .halt_reg = 0x7105c,
1232 .enable_reg = 0x7105c,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0x71054,
1250 .enable_reg = 0x71054,
1251 .enable_mask = BIT(0),
1265 .halt_reg = 0x71028,
1268 .enable_reg = 0x71028,
1269 .enable_mask = BIT(0),
1283 .halt_reg = 0x71044,
1286 .enable_reg = 0x71044,
1287 .enable_mask = BIT(0),
1301 .halt_reg = 0x71050,
1304 .enable_reg = 0x71050,
1305 .enable_mask = BIT(0),
1319 .halt_reg = 0x710a0,
1322 .enable_reg = 0x710a0,
1323 .enable_mask = BIT(0),
1337 .halt_reg = 0x7109c,
1340 .enable_reg = 0x7109c,
1341 .enable_mask = BIT(0),
1355 .halt_reg = 0x71024,
1357 .hwcg_reg = 0x71024,
1360 .enable_reg = 0x71024,
1361 .enable_mask = BIT(0),
1370 .halt_reg = 0x710a8,
1373 .enable_reg = 0x710a8,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0x710a4,
1391 .enable_reg = 0x710a4,
1392 .enable_mask = BIT(0),
1406 .halt_reg = 0x72018,
1408 .hwcg_reg = 0x72018,
1411 .enable_reg = 0x72018,
1412 .enable_mask = BIT(0),
1421 .halt_reg = 0x7205c,
1424 .enable_reg = 0x7205c,
1425 .enable_mask = BIT(0),
1439 .halt_reg = 0x72054,
1442 .enable_reg = 0x72054,
1443 .enable_mask = BIT(0),
1457 .halt_reg = 0x72028,
1460 .enable_reg = 0x72028,
1461 .enable_mask = BIT(0),
1475 .halt_reg = 0x72044,
1478 .enable_reg = 0x72044,
1479 .enable_mask = BIT(0),
1493 .halt_reg = 0x72050,
1496 .enable_reg = 0x72050,
1497 .enable_mask = BIT(0),
1511 .halt_reg = 0x720a0,
1514 .enable_reg = 0x720a0,
1515 .enable_mask = BIT(0),
1529 .halt_reg = 0x7209c,
1532 .enable_reg = 0x7209c,
1533 .enable_mask = BIT(0),
1547 .halt_reg = 0x72024,
1549 .hwcg_reg = 0x72024,
1552 .enable_reg = 0x72024,
1553 .enable_mask = BIT(0),
1562 .halt_reg = 0x720a8,
1565 .enable_reg = 0x720a8,
1566 .enable_mask = BIT(0),
1580 .halt_reg = 0x720a4,
1583 .enable_reg = 0x720a4,
1584 .enable_mask = BIT(0),
1598 .halt_reg = 0x98108,
1601 .enable_reg = 0x98108,
1602 .enable_mask = BIT(0),
1611 .halt_reg = 0x9810c,
1614 .enable_reg = 0x9810c,
1615 .enable_mask = BIT(0),
1624 .halt_reg = 0x47000,
1627 .enable_reg = 0x47000,
1628 .enable_mask = BIT(0),
1642 .halt_reg = 0x48000,
1645 .enable_reg = 0x48000,
1646 .enable_mask = BIT(0),
1660 .halt_reg = 0x49000,
1663 .enable_reg = 0x49000,
1664 .enable_mask = BIT(0),
1678 .halt_reg = 0x98004,
1681 .enable_reg = 0x98004,
1682 .enable_mask = BIT(0),
1691 .halt_reg = 0x67038,
1694 .enable_reg = 0x7d010,
1709 .halt_reg = 0x67034,
1711 .hwcg_reg = 0x67034,
1714 .enable_reg = 0x7d010,
1724 .halt_reg = 0x98114,
1727 .enable_reg = 0x98114,
1728 .enable_mask = BIT(0),
1737 .halt_reg = 0x67028,
1740 .enable_reg = 0x7d010,
1750 .halt_reg = 0x67068,
1753 .enable_reg = 0x7d010,
1768 .halt_reg = 0x6705c,
1771 .enable_reg = 0x7d010,
1786 .halt_reg = 0x6708c,
1789 .enable_reg = 0x7d020,
1804 .halt_reg = 0x6701c,
1807 .enable_reg = 0x7d010,
1817 .halt_reg = 0x67018,
1820 .enable_reg = 0x7d010,
1830 .halt_reg = 0x68058,
1833 .enable_reg = 0x7d010,
1848 .halt_reg = 0x68034,
1850 .hwcg_reg = 0x68034,
1853 .enable_reg = 0x7d010,
1863 .halt_reg = 0x98110,
1866 .enable_reg = 0x98110,
1867 .enable_mask = BIT(0),
1876 .halt_reg = 0x68028,
1879 .enable_reg = 0x7d008,
1889 .halt_reg = 0x68098,
1892 .enable_reg = 0x7d010,
1907 .halt_reg = 0x6807c,
1910 .enable_reg = 0x7d010,
1925 .halt_reg = 0x6808c,
1928 .enable_reg = 0x7d020,
1943 .halt_reg = 0x6801c,
1946 .enable_reg = 0x7d010,
1956 .halt_reg = 0x68018,
1959 .enable_reg = 0x7d010,
1969 .halt_reg = 0x5303c,
1971 .hwcg_reg = 0x5303c,
1974 .enable_reg = 0x7d010,
1989 .halt_reg = 0x53034,
1991 .hwcg_reg = 0x53034,
1994 .enable_reg = 0x7d010,
2004 .halt_reg = 0x53028,
2006 .hwcg_reg = 0x53028,
2009 .enable_reg = 0x7d010,
2019 .halt_reg = 0x5304c,
2021 .hwcg_reg = 0x5304c,
2024 .enable_reg = 0x7d010,
2039 .halt_reg = 0x53038,
2041 .hwcg_reg = 0x53038,
2044 .enable_reg = 0x7d010,
2059 .halt_reg = 0x53048,
2061 .hwcg_reg = 0x53048,
2064 .enable_reg = 0x7d010,
2079 .halt_reg = 0x5301c,
2082 .enable_reg = 0x7d010,
2092 .halt_reg = 0x53018,
2094 .hwcg_reg = 0x53018,
2097 .enable_reg = 0x7d010,
2107 .halt_reg = 0x3400c,
2110 .enable_reg = 0x3400c,
2111 .enable_mask = BIT(0),
2125 .halt_reg = 0x34004,
2128 .enable_reg = 0x34004,
2129 .enable_mask = BIT(0),
2138 .halt_reg = 0x34008,
2141 .enable_reg = 0x34008,
2142 .enable_mask = BIT(0),
2151 .halt_reg = 0x2d018,
2154 .enable_reg = 0x7d008,
2164 .halt_reg = 0x2d008,
2167 .enable_reg = 0x7d008,
2177 .halt_reg = 0x6c004,
2180 .enable_reg = 0x7d008,
2195 .halt_reg = 0x6c13c,
2198 .enable_reg = 0x7d008,
2213 .halt_reg = 0x6c274,
2216 .enable_reg = 0x7d008,
2231 .halt_reg = 0x6c3ac,
2234 .enable_reg = 0x7d008,
2249 .halt_reg = 0x6c4e4,
2252 .enable_reg = 0x7d008,
2267 .halt_reg = 0x6c61c,
2270 .enable_reg = 0x7d008,
2285 .halt_reg = 0x6c754,
2288 .enable_reg = 0x7d008,
2303 .halt_reg = 0x6c88c,
2306 .enable_reg = 0x7d008,
2321 .halt_reg = 0x6c9c4,
2324 .enable_reg = 0x7d020,
2339 .halt_reg = 0x2d000,
2341 .hwcg_reg = 0x2d000,
2344 .enable_reg = 0x7d008,
2354 .halt_reg = 0x2d004,
2356 .hwcg_reg = 0x2d004,
2359 .enable_reg = 0x7d008,
2369 .halt_reg = 0x6b004,
2372 .enable_reg = 0x6b004,
2373 .enable_mask = BIT(0),
2382 .halt_reg = 0x6b008,
2385 .enable_reg = 0x6b008,
2386 .enable_mask = BIT(0),
2400 .halt_reg = 0x6a010,
2403 .enable_reg = 0x6a010,
2404 .enable_mask = BIT(0),
2413 .halt_reg = 0x6a004,
2416 .enable_reg = 0x6a004,
2417 .enable_mask = BIT(0),
2431 .halt_reg = 0x98008,
2434 .enable_reg = 0x98008,
2435 .enable_mask = BIT(0),
2444 .halt_reg = 0x27018,
2447 .enable_reg = 0x27018,
2448 .enable_mask = BIT(0),
2462 .halt_reg = 0x27030,
2465 .enable_reg = 0x27030,
2466 .enable_mask = BIT(0),
2480 .halt_reg = 0x27024,
2483 .enable_reg = 0x27024,
2484 .enable_mask = BIT(0),
2493 .halt_reg = 0x2702c,
2496 .enable_reg = 0x2702c,
2497 .enable_mask = BIT(0),
2506 .halt_reg = 0x27028,
2509 .enable_reg = 0x27028,
2510 .enable_mask = BIT(0),
2519 .halt_reg = 0x27068,
2522 .enable_reg = 0x27068,
2523 .enable_mask = BIT(0),
2537 .halt_reg = 0x2706c,
2539 .hwcg_reg = 0x2706c,
2542 .enable_reg = 0x2706c,
2543 .enable_mask = BIT(0),
2557 .halt_reg = 0x98000,
2560 .enable_reg = 0x98000,
2561 .enable_mask = BIT(0),
2570 .halt_reg = 0x29004,
2572 .hwcg_reg = 0x29004,
2575 .enable_reg = 0x29004,
2576 .enable_mask = BIT(0),
2585 .gdscr = 0x71004,
2586 .en_rest_wait_val = 0x2,
2587 .en_few_wait_val = 0x2,
2588 .clk_dis_wait_val = 0xf,
2597 .gdscr = 0x72004,
2598 .en_rest_wait_val = 0x2,
2599 .en_few_wait_val = 0x2,
2600 .clk_dis_wait_val = 0xf,
2609 .gdscr = 0x67004,
2610 .en_rest_wait_val = 0x2,
2611 .en_few_wait_val = 0x2,
2612 .clk_dis_wait_val = 0xf,
2621 .gdscr = 0x56004,
2622 .en_rest_wait_val = 0x2,
2623 .en_few_wait_val = 0x2,
2624 .clk_dis_wait_val = 0x2,
2633 .gdscr = 0x68004,
2634 .en_rest_wait_val = 0x2,
2635 .en_few_wait_val = 0x2,
2636 .clk_dis_wait_val = 0xf,
2645 .gdscr = 0x6e004,
2646 .en_rest_wait_val = 0x2,
2647 .en_few_wait_val = 0x2,
2648 .clk_dis_wait_val = 0x2,
2657 .gdscr = 0x53004,
2658 .en_rest_wait_val = 0x2,
2659 .en_few_wait_val = 0x2,
2660 .clk_dis_wait_val = 0xf,
2669 .gdscr = 0x54004,
2670 .en_rest_wait_val = 0x2,
2671 .en_few_wait_val = 0x2,
2672 .clk_dis_wait_val = 0x2,
2681 .gdscr = 0x27004,
2682 .en_rest_wait_val = 0x2,
2683 .en_few_wait_val = 0x2,
2684 .clk_dis_wait_val = 0xf,
2693 .gdscr = 0x28008,
2694 .en_rest_wait_val = 0x2,
2695 .en_few_wait_val = 0x2,
2696 .clk_dis_wait_val = 0x2,
2862 [GCC_EMAC0_BCR] = { 0x71000 },
2863 [GCC_EMAC0_RGMII_CLK_ARES] = { 0x71050, 2 },
2864 [GCC_EMAC1_BCR] = { 0x72000 },
2865 [GCC_EMMC_BCR] = { 0x6b000 },
2866 [GCC_PCIE_1_BCR] = { 0x67000 },
2867 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e700 },
2868 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x56120 },
2869 [GCC_PCIE_1_PHY_BCR] = { 0x56000 },
2870 [GCC_PCIE_2_BCR] = { 0x68000 },
2871 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x9f700 },
2872 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x6e130 },
2873 [GCC_PCIE_2_PHY_BCR] = { 0x6e000 },
2874 [GCC_PCIE_BCR] = { 0x53000 },
2875 [GCC_PCIE_LINK_DOWN_BCR] = { 0x87000 },
2876 [GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x88008 },
2877 [GCC_PCIE_PHY_BCR] = { 0x54000 },
2878 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x88000 },
2879 [GCC_PCIE_PHY_COM_BCR] = { 0x88004 },
2880 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x8800c },
2881 [GCC_QUSB2PHY_BCR] = { 0x2a000 },
2882 [GCC_TCSR_PCIE_BCR] = { 0x84000 },
2883 [GCC_USB30_BCR] = { 0x27000 },
2884 [GCC_USB3_PHY_BCR] = { 0x28000 },
2885 [GCC_USB3PHY_PHY_BCR] = { 0x28004 },
2886 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x29000 },
2905 .max_register = 0x1f41f0,
2940 qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */ in gcc_sdx75_probe()
2941 qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */ in gcc_sdx75_probe()