Lines Matching +full:0 +full:x78000
36 .offset = 0x0,
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
73 { P_BI_TCXO, 0 },
91 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
119 { P_PCIE_PIPE_CLK, 0 },
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
139 .reg = 0x43060,
140 .shift = 0,
156 .reg = 0x43044,
157 .shift = 0,
171 .reg = 0x1706c,
172 .shift = 0,
186 F(9600000, P_BI_TCXO, 2, 0, 0),
187 F(19200000, P_BI_TCXO, 1, 0, 0),
188 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
193 .cmd_rcgr = 0x1c024,
209 F(4800000, P_BI_TCXO, 4, 0, 0),
210 F(9600000, P_BI_TCXO, 2, 0, 0),
212 F(19200000, P_BI_TCXO, 1, 0, 0),
215 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
220 .cmd_rcgr = 0x1c00c,
235 .cmd_rcgr = 0x1e024,
250 .cmd_rcgr = 0x1e00c,
265 .cmd_rcgr = 0x20024,
280 .cmd_rcgr = 0x2000c,
295 .cmd_rcgr = 0x22024,
310 .cmd_rcgr = 0x2200c,
327 F(9600000, P_BI_TCXO, 2, 0, 0),
330 F(19200000, P_BI_TCXO, 1, 0, 0),
343 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
345 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
349 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
350 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
355 .cmd_rcgr = 0x1d00c,
370 .cmd_rcgr = 0x1f00c,
385 .cmd_rcgr = 0x2100c,
400 .cmd_rcgr = 0x2300c,
415 F(19200000, P_BI_TCXO, 1, 0, 0),
416 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
417 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
418 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
423 .cmd_rcgr = 0x3000c,
424 .mnd_width = 0,
438 F(19200000, P_BI_TCXO, 1, 0, 0),
439 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
440 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
441 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
446 .cmd_rcgr = 0x37004,
461 .cmd_rcgr = 0x38004,
476 .cmd_rcgr = 0x39004,
491 F(19200000, P_BI_TCXO, 1, 0, 0),
496 .cmd_rcgr = 0x43048,
511 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
516 .cmd_rcgr = 0x43064,
517 .mnd_width = 0,
531 F(19200000, P_BI_TCXO, 1, 0, 0),
532 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
537 .cmd_rcgr = 0x24010,
538 .mnd_width = 0,
553 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
554 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
555 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
556 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
561 .cmd_rcgr = 0x1a010,
576 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
581 .cmd_rcgr = 0x17030,
596 .cmd_rcgr = 0x17048,
597 .mnd_width = 0,
612 F(19200000, P_BI_TCXO, 1, 0, 0),
617 .cmd_rcgr = 0x17070,
632 .reg = 0x30024,
633 .shift = 0,
647 .reg = 0x17060,
648 .shift = 0,
662 .halt_reg = 0x2e004,
665 .enable_reg = 0x2e004,
666 .enable_mask = BIT(0),
675 .halt_reg = 0x1b004,
678 .enable_reg = 0x6d008,
688 .halt_reg = 0x1c008,
691 .enable_reg = 0x1c008,
692 .enable_mask = BIT(0),
706 .halt_reg = 0x1c004,
709 .enable_reg = 0x1c004,
710 .enable_mask = BIT(0),
724 .halt_reg = 0x1e008,
727 .enable_reg = 0x1e008,
728 .enable_mask = BIT(0),
742 .halt_reg = 0x1e004,
745 .enable_reg = 0x1e004,
746 .enable_mask = BIT(0),
760 .halt_reg = 0x20008,
763 .enable_reg = 0x20008,
764 .enable_mask = BIT(0),
778 .halt_reg = 0x20004,
781 .enable_reg = 0x20004,
782 .enable_mask = BIT(0),
796 .halt_reg = 0x22008,
799 .enable_reg = 0x22008,
800 .enable_mask = BIT(0),
814 .halt_reg = 0x22004,
817 .enable_reg = 0x22004,
818 .enable_mask = BIT(0),
832 .halt_reg = 0x1b00c,
835 .enable_reg = 0x6d008,
845 .halt_reg = 0x1d004,
848 .enable_reg = 0x1d004,
849 .enable_mask = BIT(0),
863 .halt_reg = 0x1f004,
866 .enable_reg = 0x1f004,
867 .enable_mask = BIT(0),
881 .halt_reg = 0x21004,
884 .enable_reg = 0x21004,
885 .enable_mask = BIT(0),
899 .halt_reg = 0x23004,
902 .enable_reg = 0x23004,
903 .enable_mask = BIT(0),
917 .halt_reg = 0x27004,
919 .hwcg_reg = 0x27004,
922 .enable_reg = 0x6d008,
932 .halt_reg = 0x37000,
935 .enable_reg = 0x37000,
936 .enable_mask = BIT(0),
950 .halt_reg = 0x38000,
953 .enable_reg = 0x38000,
954 .enable_mask = BIT(0),
968 .halt_reg = 0x39000,
971 .enable_reg = 0x39000,
972 .enable_mask = BIT(0),
986 .halt_reg = 0x88004,
995 .enable_reg = 0x88004,
996 .enable_mask = BIT(0),
1005 .halt_reg = 0x43034,
1013 .hwcg_reg = 0x43034,
1016 .enable_reg = 0x6d010,
1031 .halt_reg = 0x4302c,
1033 .hwcg_reg = 0x4302c,
1036 .enable_reg = 0x6d010,
1046 .halt_reg = 0x43024,
1048 .hwcg_reg = 0x43024,
1051 .enable_reg = 0x6d010,
1061 .halt_reg = 0x4303c,
1069 .hwcg_reg = 0x4303c,
1072 .enable_reg = 0x6d010,
1087 .halt_reg = 0x43030,
1089 .hwcg_reg = 0x43030,
1092 .enable_reg = 0x6d010,
1107 .halt_reg = 0x43038,
1109 .hwcg_reg = 0x43038,
1112 .enable_reg = 0x6d010,
1127 .halt_reg = 0x4301c,
1129 .hwcg_reg = 0x4301c,
1132 .enable_reg = 0x6d010,
1133 .enable_mask = BIT(0),
1142 .halt_reg = 0x43018,
1144 .hwcg_reg = 0x43018,
1147 .enable_reg = 0x6d010,
1157 .halt_reg = 0x2400c,
1160 .enable_reg = 0x2400c,
1161 .enable_mask = BIT(0),
1175 .halt_reg = 0x24004,
1177 .hwcg_reg = 0x24004,
1180 .enable_reg = 0x24004,
1181 .enable_mask = BIT(0),
1190 .halt_reg = 0x24008,
1193 .enable_reg = 0x24008,
1194 .enable_mask = BIT(0),
1203 .halt_reg = 0x88008,
1206 .enable_reg = 0x88008,
1207 .enable_mask = BIT(0),
1216 .halt_reg = 0x1a00c,
1219 .enable_reg = 0x1a00c,
1220 .enable_mask = BIT(0),
1229 .halt_reg = 0x1a004,
1232 .enable_reg = 0x1a004,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0x17018,
1250 .enable_reg = 0x17018,
1251 .enable_mask = BIT(0),
1265 .halt_reg = 0x1702c,
1268 .enable_reg = 0x1702c,
1269 .enable_mask = BIT(0),
1283 .halt_reg = 0x17020,
1286 .enable_reg = 0x17020,
1287 .enable_mask = BIT(0),
1296 .halt_reg = 0x17028,
1299 .enable_reg = 0x17028,
1300 .enable_mask = BIT(0),
1309 .halt_reg = 0x17024,
1312 .enable_reg = 0x17024,
1313 .enable_mask = BIT(0),
1322 .halt_reg = 0x17064,
1325 .enable_reg = 0x17064,
1326 .enable_mask = BIT(0),
1340 .gdscr = 0x17004,
1348 .gdscr = 0x43004,
1356 .halt_reg = 0x17068,
1364 .hwcg_reg = 0x17068,
1367 .enable_reg = 0x17068,
1368 .enable_mask = BIT(0),
1382 .halt_reg = 0x88000,
1385 .enable_reg = 0x88000,
1386 .enable_mask = BIT(0),
1395 .halt_reg = 0x19008,
1397 .hwcg_reg = 0x19008,
1400 .enable_reg = 0x19008,
1401 .enable_mask = BIT(0),
1410 .halt_reg = 0x2e010,
1413 .enable_reg = 0x2e010,
1414 .enable_mask = BIT(0),
1423 .halt_reg = 0x2e008,
1425 .hwcg_reg = 0x2e008,
1428 .enable_reg = 0x2e008,
1429 .enable_mask = BIT(0),
1516 [GCC_BLSP1_QUP1_BCR] = { 0x1c000 },
1517 [GCC_BLSP1_QUP2_BCR] = { 0x1e000 },
1518 [GCC_BLSP1_QUP3_BCR] = { 0x20000 },
1519 [GCC_BLSP1_QUP4_BCR] = { 0x22000 },
1520 [GCC_BLSP1_UART1_BCR] = { 0x1d000 },
1521 [GCC_BLSP1_UART2_BCR] = { 0x1f000 },
1522 [GCC_BLSP1_UART3_BCR] = { 0x21000 },
1523 [GCC_BLSP1_UART4_BCR] = { 0x23000 },
1524 [GCC_PCIE_BCR] = { 0x43000 },
1525 [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
1526 [GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x78008 },
1527 [GCC_PCIE_PHY_BCR] = { 0x44000 },
1528 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x78000 },
1529 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
1530 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x7800c },
1531 [GCC_PDM_BCR] = { 0x24000 },
1532 [GCC_QUSB2PHY_BCR] = { 0x19000 },
1533 [GCC_SDCC1_BCR] = { 0x1a000 },
1534 [GCC_TCSR_PCIE_BCR] = { 0x57000 },
1535 [GCC_USB30_BCR] = { 0x17000 },
1536 [GCC_USB3_PHY_BCR] = { 0x18000 },
1537 [GCC_USB3PHY_PHY_BCR] = { 0x18004 },
1538 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x19004 },
1550 .max_register = 0x1f101c,
1579 qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ in gcc_sdx65_probe()
1580 regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ in gcc_sdx65_probe()
1581 regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ in gcc_sdx65_probe()