Lines Matching +full:0 +full:xf004
33 { 249600000, 2000000000, 0 },
37 .offset = 0x0,
42 .enable_reg = 0x6d000,
43 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x76000,
86 .enable_reg = 0x6d000,
100 .offset = 0x76000,
117 .offset = 0x74000,
122 .enable_reg = 0x6d000,
136 { P_BI_TCXO, 0 },
154 { P_BI_TCXO, 0 },
170 { P_BI_TCXO, 0 },
184 { P_BI_TCXO, 0 },
194 { P_BI_TCXO, 0 },
208 F(9600000, P_BI_TCXO, 2, 0, 0),
209 F(19200000, P_BI_TCXO, 1, 0, 0),
210 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
215 .cmd_rcgr = 0x11024,
230 F(4800000, P_BI_TCXO, 4, 0, 0),
231 F(9600000, P_BI_TCXO, 2, 0, 0),
233 F(19200000, P_BI_TCXO, 1, 0, 0),
236 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
241 .cmd_rcgr = 0x1100c,
255 .cmd_rcgr = 0x13024,
269 .cmd_rcgr = 0x1300c,
283 .cmd_rcgr = 0x15024,
297 .cmd_rcgr = 0x1500c,
311 .cmd_rcgr = 0x17024,
325 .cmd_rcgr = 0x1700c,
341 F(9600000, P_BI_TCXO, 2, 0, 0),
344 F(19200000, P_BI_TCXO, 1, 0, 0),
357 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
359 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
363 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
364 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
369 .cmd_rcgr = 0x1200c,
383 .cmd_rcgr = 0x1400c,
397 .cmd_rcgr = 0x1600c,
411 .cmd_rcgr = 0x1800c,
425 F(19200000, P_BI_TCXO, 1, 0, 0),
426 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
427 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
428 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
433 .cmd_rcgr = 0x24010,
434 .mnd_width = 0,
447 F(19200000, P_BI_TCXO, 1, 0, 0),
452 .cmd_rcgr = 0x2402c,
453 .mnd_width = 0,
468 F(19200000, P_BI_TCXO, 1, 0, 0),
469 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
470 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
471 F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0),
476 .cmd_rcgr = 0x47020,
490 F(19200000, P_BI_TCXO, 1, 0, 0),
491 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
492 F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),
497 .cmd_rcgr = 0x47038,
498 .mnd_width = 0,
511 F(19200000, P_BI_TCXO, 1, 0, 0),
512 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
513 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
514 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
515 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
520 .cmd_rcgr = 0x2b004,
534 .cmd_rcgr = 0x2c004,
548 .cmd_rcgr = 0x2d004,
562 .cmd_rcgr = 0x37034,
576 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
581 .cmd_rcgr = 0x37050,
582 .mnd_width = 0,
595 F(9600000, P_BI_TCXO, 2, 0, 0),
596 F(19200000, P_BI_TCXO, 1, 0, 0),
597 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
602 .cmd_rcgr = 0x19010,
603 .mnd_width = 0,
616 .cmd_rcgr = 0xf00c,
630 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
635 .cmd_rcgr = 0xb024,
649 F(19200000, P_BI_TCXO, 1, 0, 0),
654 .cmd_rcgr = 0xb03c,
655 .mnd_width = 0,
669 F(19200000, P_BI_TCXO, 1, 0, 0),
674 .cmd_rcgr = 0xb064,
688 .halt_reg = 0x22004,
691 .enable_reg = 0x22004,
692 .enable_mask = BIT(0),
701 .halt_reg = 0x10004,
704 .enable_reg = 0x6d008,
714 .halt_reg = 0x11008,
717 .enable_reg = 0x11008,
718 .enable_mask = BIT(0),
731 .halt_reg = 0x11004,
734 .enable_reg = 0x11004,
735 .enable_mask = BIT(0),
748 .halt_reg = 0x13008,
751 .enable_reg = 0x13008,
752 .enable_mask = BIT(0),
765 .halt_reg = 0x13004,
768 .enable_reg = 0x13004,
769 .enable_mask = BIT(0),
782 .halt_reg = 0x15008,
785 .enable_reg = 0x15008,
786 .enable_mask = BIT(0),
799 .halt_reg = 0x15004,
802 .enable_reg = 0x15004,
803 .enable_mask = BIT(0),
816 .halt_reg = 0x17008,
819 .enable_reg = 0x17008,
820 .enable_mask = BIT(0),
833 .halt_reg = 0x17004,
836 .enable_reg = 0x17004,
837 .enable_mask = BIT(0),
850 .halt_reg = 0x12004,
853 .enable_reg = 0x12004,
854 .enable_mask = BIT(0),
867 .halt_reg = 0x14004,
870 .enable_reg = 0x14004,
871 .enable_mask = BIT(0),
884 .halt_reg = 0x16004,
887 .enable_reg = 0x16004,
888 .enable_mask = BIT(0),
901 .halt_reg = 0x18004,
904 .enable_reg = 0x18004,
905 .enable_mask = BIT(0),
918 .halt_reg = 0x1c004,
920 .hwcg_reg = 0x1c004,
923 .enable_reg = 0x6d008,
933 .halt_reg = 0x2100c,
935 .hwcg_reg = 0x2100c,
938 .enable_reg = 0x6d008,
948 .halt_reg = 0x21008,
951 .enable_reg = 0x6d008,
961 .halt_reg = 0x21004,
964 .enable_reg = 0x6d008,
974 .halt_reg = 0x24008,
977 .enable_reg = 0x24008,
978 .enable_mask = BIT(0),
991 .halt_reg = 0x4701c,
994 .enable_reg = 0x4701c,
995 .enable_mask = BIT(0),
1004 .halt_reg = 0x47018,
1007 .enable_reg = 0x47018,
1008 .enable_mask = BIT(0),
1021 .halt_reg = 0x47010,
1024 .enable_reg = 0x47010,
1025 .enable_mask = BIT(0),
1038 .halt_reg = 0x47014,
1041 .enable_reg = 0x47014,
1042 .enable_mask = BIT(0),
1051 .halt_reg = 0x2b000,
1054 .enable_reg = 0x2b000,
1055 .enable_mask = BIT(0),
1068 .halt_reg = 0x2c000,
1071 .enable_reg = 0x2c000,
1072 .enable_mask = BIT(0),
1085 .halt_reg = 0x2d000,
1088 .enable_reg = 0x2d000,
1089 .enable_mask = BIT(0),
1102 .halt_reg = 0x88004,
1105 .enable_reg = 0x88004,
1106 .enable_mask = BIT(0),
1115 .halt_reg = 0x37024,
1118 .enable_reg = 0x6d010,
1128 .halt_reg = 0x3701c,
1131 .enable_reg = 0x6d010,
1141 .halt_reg = 0x37018,
1144 .enable_reg = 0x6d010,
1154 .halt_reg = 0x3702c,
1157 .enable_reg = 0x6d010,
1167 .halt_reg = 0x37020,
1170 .enable_reg = 0x6d010,
1184 .halt_reg = 0x37028,
1187 .enable_reg = 0x6d010,
1201 .halt_reg = 0x37014,
1203 .hwcg_reg = 0x37014,
1206 .enable_reg = 0x6d010,
1207 .enable_mask = BIT(0),
1216 .halt_reg = 0x37010,
1219 .enable_reg = 0x6d010,
1229 .halt_reg = 0x1900c,
1232 .enable_reg = 0x1900c,
1233 .enable_mask = BIT(0),
1246 .halt_reg = 0x19004,
1248 .hwcg_reg = 0x19004,
1251 .enable_reg = 0x19004,
1252 .enable_mask = BIT(0),
1261 .halt_reg = 0x19008,
1264 .enable_reg = 0x19008,
1265 .enable_mask = BIT(0),
1274 .halt_reg = 0xf008,
1277 .enable_reg = 0xf008,
1278 .enable_mask = BIT(0),
1287 .halt_reg = 0xf004,
1290 .enable_reg = 0xf004,
1291 .enable_mask = BIT(0),
1304 .halt_reg = 0xb010,
1307 .enable_reg = 0xb010,
1308 .enable_mask = BIT(0),
1321 .halt_reg = 0xb020,
1324 .enable_reg = 0xb020,
1325 .enable_mask = BIT(0),
1338 .halt_reg = 0xb014,
1341 .enable_reg = 0xb014,
1342 .enable_mask = BIT(0),
1351 .halt_reg = 0xb01c,
1354 .enable_reg = 0xb01c,
1355 .enable_mask = BIT(0),
1364 .halt_reg = 0xb018,
1367 .enable_reg = 0xb018,
1368 .enable_mask = BIT(0),
1377 .halt_reg = 0xb058,
1380 .enable_reg = 0xb058,
1381 .enable_mask = BIT(0),
1394 .halt_reg = 0xb05c,
1397 .enable_reg = 0xb05c,
1398 .enable_mask = BIT(0),
1407 .halt_reg = 0x88000,
1410 .enable_reg = 0x88000,
1411 .enable_mask = BIT(0),
1420 .halt_reg = 0xe004,
1422 .hwcg_reg = 0xe004,
1425 .enable_reg = 0xe004,
1426 .enable_mask = BIT(0),
1435 .halt_reg = 0x22008,
1438 .enable_reg = 0x22008,
1439 .enable_mask = BIT(0),
1448 .gdscr = 0x0b004,
1456 .gdscr = 0x37004,
1464 .gdscr = 0x47004,
1564 [GCC_EMAC_BCR] = { 0x47000 },
1565 [GCC_PCIE_BCR] = { 0x37000 },
1566 [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
1567 [GCC_PCIE_PHY_BCR] = { 0x39000 },
1568 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
1569 [GCC_QUSB2PHY_BCR] = { 0xd000 },
1570 [GCC_USB30_BCR] = { 0xb000 },
1571 [GCC_USB3_PHY_BCR] = { 0xc000 },
1572 [GCC_USB3PHY_PHY_BCR] = { 0xc004 },
1573 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 },
1586 .max_register = 0x9b040,
1615 qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ in gcc_sdx55_probe()
1616 regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ in gcc_sdx55_probe()
1617 regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ in gcc_sdx55_probe()