Lines Matching +full:0 +full:x50004
38 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x76000,
58 .enable_reg = 0x52000,
72 .offset = 0x13000,
75 .enable_reg = 0x52000,
89 { 0x0, 1 },
90 { 0x1, 2 },
91 { 0x3, 4 },
92 { 0x7, 8 },
97 .offset = 0x0,
114 { P_BI_TCXO, 0 },
126 { P_BI_TCXO, 0 },
140 { P_BI_TCXO, 0 },
150 { P_BI_TCXO, 0 },
160 { P_BI_TCXO, 0 },
168 { P_BI_TCXO, 0 },
201 { P_BI_TCXO, 0 },
215 { P_BI_TCXO, 0 },
229 F(19200000, P_BI_TCXO, 1, 0, 0),
234 .cmd_rcgr = 0x48014,
235 .mnd_width = 0,
248 F(19200000, P_BI_TCXO, 1, 0, 0),
253 .cmd_rcgr = 0x4815c,
254 .mnd_width = 0,
267 F(19200000, P_BI_TCXO, 1, 0, 0),
268 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
273 .cmd_rcgr = 0x4815c,
274 .mnd_width = 0,
287 F(19200000, P_BI_TCXO, 1, 0, 0),
288 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
289 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
290 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
291 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
296 .cmd_rcgr = 0x64004,
310 .cmd_rcgr = 0x65004,
324 .cmd_rcgr = 0x66004,
338 F(9600000, P_BI_TCXO, 2, 0, 0),
339 F(19200000, P_BI_TCXO, 1, 0, 0),
344 .cmd_rcgr = 0x6b028,
358 .cmd_rcgr = 0x8d028,
372 F(19200000, P_BI_TCXO, 1, 0, 0),
373 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
378 .cmd_rcgr = 0x6f014,
379 .mnd_width = 0,
392 F(19200000, P_BI_TCXO, 1, 0, 0),
393 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
394 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
395 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
400 .cmd_rcgr = 0x4b008,
401 .mnd_width = 0,
414 F(9600000, P_BI_TCXO, 2, 0, 0),
415 F(19200000, P_BI_TCXO, 1, 0, 0),
416 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
421 .cmd_rcgr = 0x33010,
422 .mnd_width = 0,
437 F(19200000, P_BI_TCXO, 1, 0, 0),
444 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
448 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
461 .cmd_rcgr = 0x17034,
477 .cmd_rcgr = 0x17164,
493 .cmd_rcgr = 0x17294,
509 .cmd_rcgr = 0x173c4,
525 .cmd_rcgr = 0x174f4,
541 .cmd_rcgr = 0x17624,
557 .cmd_rcgr = 0x17754,
573 .cmd_rcgr = 0x17884,
589 .cmd_rcgr = 0x18018,
605 .cmd_rcgr = 0x18148,
621 .cmd_rcgr = 0x18278,
637 .cmd_rcgr = 0x183a8,
653 .cmd_rcgr = 0x184d8,
669 .cmd_rcgr = 0x18608,
685 .cmd_rcgr = 0x18738,
701 .cmd_rcgr = 0x18868,
714 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
715 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
716 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
717 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
722 .cmd_rcgr = 0x26028,
736 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
737 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
738 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
739 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
744 .cmd_rcgr = 0x26010,
759 F(9600000, P_BI_TCXO, 2, 0, 0),
760 F(19200000, P_BI_TCXO, 1, 0, 0),
761 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
762 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
763 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
764 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
769 .cmd_rcgr = 0x1400c,
784 F(9600000, P_BI_TCXO, 2, 0, 0),
785 F(19200000, P_BI_TCXO, 1, 0, 0),
787 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
788 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
793 .cmd_rcgr = 0x1600c,
808 F(9600000, P_BI_TCXO, 2, 0, 0),
809 F(19200000, P_BI_TCXO, 1, 0, 0),
810 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
811 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
812 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
813 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
818 .cmd_rcgr = 0x1600c,
837 .cmd_rcgr = 0x36010,
851 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
852 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
853 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
854 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
855 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
860 .cmd_rcgr = 0x7501c,
874 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
875 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
876 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
877 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
882 .cmd_rcgr = 0x7505c,
883 .mnd_width = 0,
896 .cmd_rcgr = 0x75090,
897 .mnd_width = 0,
910 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
911 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
912 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
917 .cmd_rcgr = 0x75074,
918 .mnd_width = 0,
931 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
932 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
933 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
934 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
935 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
940 .cmd_rcgr = 0x7701c,
954 .cmd_rcgr = 0x7705c,
955 .mnd_width = 0,
968 .cmd_rcgr = 0x77090,
969 .mnd_width = 0,
982 .cmd_rcgr = 0x77074,
983 .mnd_width = 0,
996 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
997 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
998 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
999 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1000 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1005 .cmd_rcgr = 0xf018,
1019 F(19200000, P_BI_TCXO, 1, 0, 0),
1020 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1021 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1022 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1027 .cmd_rcgr = 0xf030,
1028 .mnd_width = 0,
1041 .cmd_rcgr = 0x10018,
1055 .cmd_rcgr = 0x10030,
1056 .mnd_width = 0,
1069 .cmd_rcgr = 0xf05c,
1070 .mnd_width = 0,
1083 .cmd_rcgr = 0x1005c,
1084 .mnd_width = 0,
1097 .cmd_rcgr = 0x7a030,
1098 .mnd_width = 0,
1111 F(19200000, P_BI_TCXO, 1, 0, 0),
1112 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1113 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
1118 .cmd_rcgr = 0x7a018,
1119 .mnd_width = 0,
1132 .halt_reg = 0x90014,
1135 .enable_reg = 0x90014,
1136 .enable_mask = BIT(0),
1145 .halt_reg = 0x82028,
1147 .hwcg_reg = 0x82028,
1150 .enable_reg = 0x82028,
1151 .enable_mask = BIT(0),
1165 .halt_reg = 0x82024,
1167 .hwcg_reg = 0x82024,
1170 .enable_reg = 0x82024,
1171 .enable_mask = BIT(0),
1185 .halt_reg = 0x8201c,
1188 .enable_reg = 0x8201c,
1189 .enable_mask = BIT(0),
1203 .halt_reg = 0x82020,
1206 .enable_reg = 0x82020,
1207 .enable_mask = BIT(0),
1221 .halt_reg = 0x7a050,
1224 .enable_reg = 0x7a050,
1225 .enable_mask = BIT(0),
1239 .halt_reg = 0x38004,
1241 .hwcg_reg = 0x38004,
1244 .enable_reg = 0x52004,
1254 .halt_reg = 0xb008,
1256 .hwcg_reg = 0xb008,
1259 .enable_reg = 0xb008,
1260 .enable_mask = BIT(0),
1270 .halt_reg = 0xb020,
1273 .enable_reg = 0xb020,
1274 .enable_mask = BIT(0),
1283 .halt_reg = 0xb02c,
1286 .enable_reg = 0xb02c,
1287 .enable_mask = BIT(0),
1297 .halt_reg = 0x4100c,
1299 .hwcg_reg = 0x4100c,
1302 .enable_reg = 0x52004,
1312 .halt_reg = 0x41008,
1315 .enable_reg = 0x52004,
1325 .halt_reg = 0x41004,
1328 .enable_reg = 0x52004,
1338 .halt_reg = 0x502c,
1341 .enable_reg = 0x502c,
1342 .enable_mask = BIT(0),
1356 .halt_reg = 0x5030,
1359 .enable_reg = 0x5030,
1360 .enable_mask = BIT(0),
1374 .halt_reg = 0x48000,
1377 .enable_reg = 0x52004,
1392 .halt_reg = 0x48008,
1395 .enable_reg = 0x48008,
1396 .enable_mask = BIT(0),
1414 .halt_reg = 0x48008,
1417 .enable_reg = 0x48008,
1418 .enable_mask = BIT(0),
1432 .halt_reg = 0x44038,
1435 .enable_reg = 0x44038,
1436 .enable_mask = BIT(0),
1445 .halt_reg = 0xb00c,
1447 .hwcg_reg = 0xb00c,
1450 .enable_reg = 0xb00c,
1451 .enable_mask = BIT(0),
1461 .halt_reg = 0xb024,
1464 .enable_reg = 0xb024,
1465 .enable_mask = BIT(0),
1476 .enable_reg = 0x52004,
1492 .enable_reg = 0x52004,
1506 .halt_reg = 0xb030,
1509 .enable_reg = 0xb030,
1510 .enable_mask = BIT(0),
1520 .halt_reg = 0x64000,
1523 .enable_reg = 0x64000,
1524 .enable_mask = BIT(0),
1538 .halt_reg = 0x65000,
1541 .enable_reg = 0x65000,
1542 .enable_mask = BIT(0),
1556 .halt_reg = 0x66000,
1559 .enable_reg = 0x66000,
1560 .enable_mask = BIT(0),
1574 .halt_reg = 0x71004,
1576 .hwcg_reg = 0x71004,
1579 .enable_reg = 0x71004,
1580 .enable_mask = BIT(0),
1592 .enable_reg = 0x52004,
1608 .enable_reg = 0x52004,
1622 .halt_reg = 0x8c010,
1625 .enable_reg = 0x8c010,
1626 .enable_mask = BIT(0),
1635 .halt_reg = 0x7100c,
1638 .enable_reg = 0x7100c,
1639 .enable_mask = BIT(0),
1648 .halt_reg = 0x71018,
1651 .enable_reg = 0x71018,
1652 .enable_mask = BIT(0),
1661 .halt_reg = 0x7a04c,
1664 .enable_reg = 0x7a04c,
1665 .enable_mask = BIT(0),
1679 .halt_reg = 0x8a008,
1682 .enable_reg = 0x8a008,
1683 .enable_mask = BIT(0),
1692 .halt_reg = 0x8a000,
1694 .hwcg_reg = 0x8a000,
1697 .enable_reg = 0x8a000,
1698 .enable_mask = BIT(0),
1709 .enable_reg = 0x52004,
1719 .halt_reg = 0x8a004,
1721 .hwcg_reg = 0x8a004,
1724 .enable_reg = 0x8a004,
1725 .enable_mask = BIT(0),
1734 .halt_reg = 0x8a154,
1737 .enable_reg = 0x8a154,
1738 .enable_mask = BIT(0),
1747 .halt_reg = 0x8a150,
1750 .enable_reg = 0x8a150,
1751 .enable_mask = BIT(0),
1760 .halt_reg = 0x7a048,
1763 .enable_reg = 0x7a048,
1764 .enable_mask = BIT(0),
1778 .halt_reg = 0x6b01c,
1781 .enable_reg = 0x5200c,
1796 .halt_reg = 0x6b018,
1798 .hwcg_reg = 0x6b018,
1801 .enable_reg = 0x5200c,
1811 .halt_reg = 0x8c00c,
1814 .enable_reg = 0x8c00c,
1815 .enable_mask = BIT(0),
1824 .halt_reg = 0x6b014,
1827 .enable_reg = 0x5200c,
1839 .enable_reg = 0x5200c,
1854 .halt_reg = 0x6b010,
1856 .hwcg_reg = 0x6b010,
1859 .enable_reg = 0x5200c,
1860 .enable_mask = BIT(0),
1869 .halt_reg = 0x6b00c,
1872 .enable_reg = 0x5200c,
1882 .halt_reg = 0x8d01c,
1885 .enable_reg = 0x52004,
1900 .halt_reg = 0x8d018,
1902 .hwcg_reg = 0x8d018,
1905 .enable_reg = 0x52004,
1915 .halt_reg = 0x8c02c,
1918 .enable_reg = 0x8c02c,
1919 .enable_mask = BIT(0),
1928 .halt_reg = 0x8d014,
1931 .enable_reg = 0x52004,
1943 .enable_reg = 0x52004,
1957 .halt_reg = 0x8d010,
1959 .hwcg_reg = 0x8d010,
1962 .enable_reg = 0x52004,
1972 .halt_reg = 0x8d00c,
1975 .enable_reg = 0x52004,
1985 .halt_reg = 0x6f004,
1988 .enable_reg = 0x6f004,
1989 .enable_mask = BIT(0),
2003 .halt_reg = 0x6f02c,
2006 .enable_reg = 0x6f02c,
2007 .enable_mask = BIT(0),
2021 .halt_reg = 0x3300c,
2024 .enable_reg = 0x3300c,
2025 .enable_mask = BIT(0),
2039 .halt_reg = 0x33004,
2041 .hwcg_reg = 0x33004,
2044 .enable_reg = 0x33004,
2045 .enable_mask = BIT(0),
2054 .halt_reg = 0x33008,
2057 .enable_reg = 0x33008,
2058 .enable_mask = BIT(0),
2067 .halt_reg = 0x34004,
2069 .hwcg_reg = 0x34004,
2072 .enable_reg = 0x52004,
2082 .halt_reg = 0xb014,
2084 .hwcg_reg = 0xb014,
2087 .enable_reg = 0xb014,
2088 .enable_mask = BIT(0),
2097 .halt_reg = 0xb018,
2099 .hwcg_reg = 0xb018,
2102 .enable_reg = 0xb018,
2103 .enable_mask = BIT(0),
2112 .halt_reg = 0xb010,
2114 .hwcg_reg = 0xb010,
2117 .enable_reg = 0xb010,
2118 .enable_mask = BIT(0),
2127 .halt_reg = 0x4b000,
2130 .enable_reg = 0x4b000,
2131 .enable_mask = BIT(0),
2140 .halt_reg = 0x4b004,
2143 .enable_reg = 0x4b004,
2144 .enable_mask = BIT(0),
2158 .halt_reg = 0x17030,
2161 .enable_reg = 0x5200c,
2176 .halt_reg = 0x17160,
2179 .enable_reg = 0x5200c,
2194 .halt_reg = 0x17290,
2197 .enable_reg = 0x5200c,
2212 .halt_reg = 0x173c0,
2215 .enable_reg = 0x5200c,
2230 .halt_reg = 0x174f0,
2233 .enable_reg = 0x5200c,
2248 .halt_reg = 0x17620,
2251 .enable_reg = 0x5200c,
2266 .halt_reg = 0x17750,
2269 .enable_reg = 0x5200c,
2284 .halt_reg = 0x17880,
2287 .enable_reg = 0x5200c,
2302 .halt_reg = 0x18014,
2305 .enable_reg = 0x5200c,
2320 .halt_reg = 0x18144,
2323 .enable_reg = 0x5200c,
2338 .halt_reg = 0x18274,
2341 .enable_reg = 0x5200c,
2356 .halt_reg = 0x183a4,
2359 .enable_reg = 0x5200c,
2374 .halt_reg = 0x184d4,
2377 .enable_reg = 0x5200c,
2392 .halt_reg = 0x18604,
2395 .enable_reg = 0x5200c,
2410 .halt_reg = 0x18734,
2413 .enable_reg = 0x5200c,
2428 .halt_reg = 0x18864,
2431 .enable_reg = 0x5200c,
2446 .halt_reg = 0x17004,
2449 .enable_reg = 0x5200c,
2459 .halt_reg = 0x17008,
2461 .hwcg_reg = 0x17008,
2464 .enable_reg = 0x5200c,
2474 .halt_reg = 0x1800c,
2477 .enable_reg = 0x5200c,
2487 .halt_reg = 0x18010,
2489 .hwcg_reg = 0x18010,
2492 .enable_reg = 0x5200c,
2502 .halt_reg = 0x26008,
2505 .enable_reg = 0x26008,
2506 .enable_mask = BIT(0),
2515 .halt_reg = 0x26004,
2518 .enable_reg = 0x26004,
2519 .enable_mask = BIT(0),
2533 .halt_reg = 0x2600c,
2536 .enable_reg = 0x2600c,
2537 .enable_mask = BIT(0),
2551 .halt_reg = 0x14008,
2554 .enable_reg = 0x14008,
2555 .enable_mask = BIT(0),
2564 .halt_reg = 0x14004,
2567 .enable_reg = 0x14004,
2568 .enable_mask = BIT(0),
2582 .halt_reg = 0x16008,
2585 .enable_reg = 0x16008,
2586 .enable_mask = BIT(0),
2595 .halt_reg = 0x16004,
2598 .enable_reg = 0x16004,
2599 .enable_mask = BIT(0),
2617 .halt_reg = 0x16004,
2620 .enable_reg = 0x16004,
2621 .enable_mask = BIT(0),
2635 .halt_reg = 0x414c,
2638 .enable_reg = 0x52004,
2639 .enable_mask = BIT(0),
2653 .halt_reg = 0x36004,
2656 .enable_reg = 0x36004,
2657 .enable_mask = BIT(0),
2666 .halt_reg = 0x3600c,
2669 .enable_reg = 0x3600c,
2670 .enable_mask = BIT(0),
2679 .halt_reg = 0x36008,
2682 .enable_reg = 0x36008,
2683 .enable_mask = BIT(0),
2697 .halt_reg = 0x75010,
2699 .hwcg_reg = 0x75010,
2702 .enable_reg = 0x75010,
2703 .enable_mask = BIT(0),
2712 .halt_reg = 0x7500c,
2714 .hwcg_reg = 0x7500c,
2717 .enable_reg = 0x7500c,
2718 .enable_mask = BIT(0),
2732 .halt_reg = 0x8c004,
2735 .enable_reg = 0x8c004,
2736 .enable_mask = BIT(0),
2745 .halt_reg = 0x75058,
2747 .hwcg_reg = 0x75058,
2750 .enable_reg = 0x75058,
2751 .enable_mask = BIT(0),
2765 .halt_reg = 0x7508c,
2767 .hwcg_reg = 0x7508c,
2770 .enable_reg = 0x7508c,
2771 .enable_mask = BIT(0),
2787 .enable_reg = 0x75018,
2788 .enable_mask = BIT(0),
2799 .enable_reg = 0x750a8,
2800 .enable_mask = BIT(0),
2811 .enable_reg = 0x75014,
2812 .enable_mask = BIT(0),
2821 .halt_reg = 0x75054,
2823 .hwcg_reg = 0x75054,
2826 .enable_reg = 0x75054,
2827 .enable_mask = BIT(0),
2841 .halt_reg = 0x8c000,
2844 .enable_reg = 0x8c000,
2845 .enable_mask = BIT(0),
2854 .halt_reg = 0x77010,
2856 .hwcg_reg = 0x77010,
2859 .enable_reg = 0x77010,
2860 .enable_mask = BIT(0),
2869 .halt_reg = 0x7700c,
2871 .hwcg_reg = 0x7700c,
2874 .enable_reg = 0x7700c,
2875 .enable_mask = BIT(0),
2889 .halt_reg = 0x77058,
2891 .hwcg_reg = 0x77058,
2894 .enable_reg = 0x77058,
2895 .enable_mask = BIT(0),
2909 .halt_reg = 0x7708c,
2911 .hwcg_reg = 0x7708c,
2914 .enable_reg = 0x7708c,
2915 .enable_mask = BIT(0),
2931 .enable_reg = 0x77018,
2932 .enable_mask = BIT(0),
2943 .enable_reg = 0x770a8,
2944 .enable_mask = BIT(0),
2955 .enable_reg = 0x77014,
2956 .enable_mask = BIT(0),
2965 .halt_reg = 0x77054,
2967 .hwcg_reg = 0x77054,
2970 .enable_reg = 0x77054,
2971 .enable_mask = BIT(0),
2985 .halt_reg = 0xf00c,
2988 .enable_reg = 0xf00c,
2989 .enable_mask = BIT(0),
3003 .halt_reg = 0xf014,
3006 .enable_reg = 0xf014,
3007 .enable_mask = BIT(0),
3021 .halt_reg = 0xf010,
3024 .enable_reg = 0xf010,
3025 .enable_mask = BIT(0),
3034 .halt_reg = 0x1000c,
3037 .enable_reg = 0x1000c,
3038 .enable_mask = BIT(0),
3052 .halt_reg = 0x10014,
3055 .enable_reg = 0x10014,
3056 .enable_mask = BIT(0),
3070 .halt_reg = 0x10010,
3073 .enable_reg = 0x10010,
3074 .enable_mask = BIT(0),
3083 .halt_reg = 0x8c008,
3086 .enable_reg = 0x8c008,
3087 .enable_mask = BIT(0),
3096 .halt_reg = 0xf04c,
3099 .enable_reg = 0xf04c,
3100 .enable_mask = BIT(0),
3114 .halt_reg = 0xf050,
3117 .enable_reg = 0xf050,
3118 .enable_mask = BIT(0),
3134 .enable_reg = 0xf054,
3135 .enable_mask = BIT(0),
3144 .halt_reg = 0x8c028,
3147 .enable_reg = 0x8c028,
3148 .enable_mask = BIT(0),
3157 .halt_reg = 0x1004c,
3160 .enable_reg = 0x1004c,
3161 .enable_mask = BIT(0),
3175 .halt_reg = 0x10050,
3178 .enable_reg = 0x10050,
3179 .enable_mask = BIT(0),
3195 .enable_reg = 0x10054,
3196 .enable_mask = BIT(0),
3205 .halt_reg = 0x6a004,
3207 .hwcg_reg = 0x6a004,
3210 .enable_reg = 0x6a004,
3211 .enable_mask = BIT(0),
3220 .halt_reg = 0x7a00c,
3223 .enable_reg = 0x7a00c,
3224 .enable_mask = BIT(0),
3238 .halt_reg = 0x7a004,
3241 .enable_reg = 0x7a004,
3242 .enable_mask = BIT(0),
3256 .halt_reg = 0x7a008,
3259 .enable_reg = 0x7a008,
3260 .enable_mask = BIT(0),
3274 .halt_reg = 0xb004,
3276 .hwcg_reg = 0xb004,
3279 .enable_reg = 0xb004,
3280 .enable_mask = BIT(0),
3290 .halt_reg = 0xb01c,
3293 .enable_reg = 0xb01c,
3294 .enable_mask = BIT(0),
3303 .halt_reg = 0xb028,
3306 .enable_reg = 0xb028,
3307 .enable_mask = BIT(0),
3317 .halt_reg = 0x7a014,
3319 .hwcg_reg = 0x7a014,
3322 .enable_reg = 0x7a014,
3323 .enable_mask = BIT(0),
3332 .halt_reg = 0x7a010,
3335 .enable_reg = 0x7a010,
3336 .enable_mask = BIT(0),
3350 .halt_reg = 0x48190,
3353 .enable_reg = 0x48190,
3354 .enable_mask = BIT(0),
3364 .halt_reg = 0x48004,
3366 .hwcg_reg = 0x48004,
3369 .enable_reg = 0x52004,
3382 .halt_reg = 0x47000,
3385 .enable_reg = 0x47000,
3386 .enable_mask = BIT(0),
3396 .halt_reg = 0x47008,
3399 .enable_reg = 0x47008,
3400 .enable_mask = BIT(0),
3411 .gdscr = 0x6b004,
3420 .gdscr = 0x8d004,
3429 .gdscr = 0x75004,
3438 .gdscr = 0x77004,
3447 .gdscr = 0xf004,
3456 .gdscr = 0x10004,
3465 .gdscr = 0x7d030,
3474 .gdscr = 0x7d03c,
3483 .gdscr = 0x7d034,
3492 .gdscr = 0x7d038,
3501 .gdscr = 0x7d040,
3510 .gdscr = 0x7d048,
3519 .gdscr = 0x7d044,
3873 [GCC_MMSS_BCR] = { 0xb000 },
3874 [GCC_PCIE_0_BCR] = { 0x6b000 },
3875 [GCC_PCIE_1_BCR] = { 0x8d000 },
3876 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3877 [GCC_PDM_BCR] = { 0x33000 },
3878 [GCC_PRNG_BCR] = { 0x34000 },
3879 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3880 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3881 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3882 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3883 [GCC_SDCC2_BCR] = { 0x14000 },
3884 [GCC_SDCC4_BCR] = { 0x16000 },
3885 [GCC_TSIF_BCR] = { 0x36000 },
3886 [GCC_UFS_CARD_BCR] = { 0x75000 },
3887 [GCC_UFS_PHY_BCR] = { 0x77000 },
3888 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3889 [GCC_USB30_SEC_BCR] = { 0x10000 },
3890 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3891 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3892 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3893 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3894 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3895 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3896 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3897 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3898 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3943 .max_register = 0x182090,
4005 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sdm845_probe()
4006 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sdm845_probe()