Lines Matching +full:0 +full:x50004
51 .offset = 0x0,
54 .enable_reg = 0x52000,
55 .enable_mask = BIT(0),
81 .offset = 0x00000,
94 .offset = 0x1000,
97 .enable_reg = 0x52000,
124 .offset = 0x1000,
137 .offset = 0x77000,
140 .enable_reg = 0x52000,
154 .offset = 0x77000,
168 { P_XO, 0 },
180 { P_XO, 0 },
190 { P_XO, 0 },
204 { P_XO, 0 },
214 { P_XO, 0 },
224 { P_XO, 0 },
242 { P_XO, 0 },
256 { P_XO, 0 },
270 F(19200000, P_XO, 1, 0, 0),
271 F(50000000, P_GPLL0, 12, 0, 0),
276 .cmd_rcgr = 0x19020,
277 .mnd_width = 0,
291 F(4800000, P_XO, 4, 0, 0),
292 F(9600000, P_XO, 2, 0, 0),
294 F(19200000, P_XO, 1, 0, 0),
296 F(50000000, P_GPLL0, 12, 0, 0),
301 .cmd_rcgr = 0x1900c,
315 .cmd_rcgr = 0x1b020,
316 .mnd_width = 0,
329 .cmd_rcgr = 0x1b00c,
343 .cmd_rcgr = 0x1d020,
344 .mnd_width = 0,
357 .cmd_rcgr = 0x1d00c,
371 .cmd_rcgr = 0x1f020,
372 .mnd_width = 0,
385 .cmd_rcgr = 0x1f00c,
403 F(19200000, P_XO, 1, 0, 0),
406 F(40000000, P_GPLL0, 15, 0, 0),
408 F(48000000, P_GPLL0, 12.5, 0, 0),
412 F(60000000, P_GPLL0, 10, 0, 0),
413 F(63157895, P_GPLL0, 9.5, 0, 0),
418 .cmd_rcgr = 0x1a00c,
432 .cmd_rcgr = 0x1c00c,
446 .cmd_rcgr = 0x26020,
447 .mnd_width = 0,
460 .cmd_rcgr = 0x2600c,
474 .cmd_rcgr = 0x28020,
475 .mnd_width = 0,
488 .cmd_rcgr = 0x2800c,
502 .cmd_rcgr = 0x2a020,
503 .mnd_width = 0,
516 .cmd_rcgr = 0x2a00c,
530 .cmd_rcgr = 0x2c020,
531 .mnd_width = 0,
544 .cmd_rcgr = 0x2c00c,
558 .cmd_rcgr = 0x2700c,
572 .cmd_rcgr = 0x2900c,
586 F(19200000, P_XO, 1, 0, 0),
587 F(100000000, P_GPLL0, 6, 0, 0),
588 F(200000000, P_GPLL0, 3, 0, 0),
593 .cmd_rcgr = 0x64004,
607 .cmd_rcgr = 0x65004,
621 .cmd_rcgr = 0x66004,
635 F(300000000, P_GPLL0, 2, 0, 0),
636 F(600000000, P_GPLL0, 1, 0, 0),
641 .cmd_rcgr = 0x4805c,
642 .mnd_width = 0,
655 F(384000000, P_GPLL4, 4, 0, 0),
656 F(768000000, P_GPLL4, 2, 0, 0),
657 F(1536000000, P_GPLL4, 1, 0, 0),
662 .cmd_rcgr = 0x48074,
663 .mnd_width = 0,
676 F(19200000, P_XO, 1, 0, 0),
681 .cmd_rcgr = 0x48044,
682 .mnd_width = 0,
695 F(60000000, P_GPLL0, 10, 0, 0),
700 .cmd_rcgr = 0x33010,
701 .mnd_width = 0,
714 F(19200000, P_XO, 1, 0, 0),
715 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
716 F(160400000, P_GPLL1, 5, 0, 0),
717 F(267333333, P_GPLL1, 3, 0, 0),
722 .cmd_rcgr = 0x4d00c,
723 .mnd_width = 0,
740 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
741 F(100000000, P_GPLL0, 6, 0, 0),
742 F(192000000, P_GPLL4, 8, 0, 0),
743 F(384000000, P_GPLL4, 4, 0, 0),
748 .cmd_rcgr = 0x1602c,
762 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
763 F(150000000, P_GPLL0, 4, 0, 0),
764 F(200000000, P_GPLL0, 3, 0, 0),
765 F(300000000, P_GPLL0, 2, 0, 0),
770 .cmd_rcgr = 0x16010,
771 .mnd_width = 0,
788 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
789 F(100000000, P_GPLL0, 6, 0, 0),
790 F(192000000, P_GPLL4, 8, 0, 0),
791 F(200000000, P_GPLL0, 3, 0, 0),
796 .cmd_rcgr = 0x14010,
810 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
811 F(100000000, P_GPLL0, 6, 0, 0),
812 F(150000000, P_GPLL0, 4, 0, 0),
813 F(200000000, P_GPLL0, 3, 0, 0),
814 F(240000000, P_GPLL0, 2.5, 0, 0),
819 .cmd_rcgr = 0x75018,
833 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
834 F(150000000, P_GPLL0, 4, 0, 0),
835 F(300000000, P_GPLL0, 2, 0, 0),
840 .cmd_rcgr = 0x76010,
841 .mnd_width = 0,
854 .cmd_rcgr = 0x76044,
855 .mnd_width = 0,
868 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
869 F(75000000, P_GPLL0, 8, 0, 0),
870 F(150000000, P_GPLL0, 4, 0, 0),
875 .cmd_rcgr = 0x76028,
876 .mnd_width = 0,
889 F(19200000, P_XO, 1, 0, 0),
890 F(60000000, P_GPLL0, 10, 0, 0),
891 F(120000000, P_GPLL0, 5, 0, 0),
896 .cmd_rcgr = 0x2f010,
910 F(19200000, P_XO, 1, 0, 0),
911 F(60000000, P_GPLL0, 10, 0, 0),
916 .cmd_rcgr = 0x2f024,
917 .mnd_width = 0,
930 F(19200000, P_XO, 1, 0, 0),
931 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
932 F(120000000, P_GPLL0, 5, 0, 0),
933 F(133333333, P_GPLL0, 4.5, 0, 0),
934 F(150000000, P_GPLL0, 4, 0, 0),
935 F(200000000, P_GPLL0, 3, 0, 0),
936 F(240000000, P_GPLL0, 2.5, 0, 0),
941 .cmd_rcgr = 0xf014,
955 F(19200000, P_XO, 1, 0, 0),
956 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
957 F(60000000, P_GPLL0, 10, 0, 0),
962 .cmd_rcgr = 0xf028,
963 .mnd_width = 0,
976 F(1200000, P_XO, 16, 0, 0),
977 F(19200000, P_XO, 1, 0, 0),
982 .cmd_rcgr = 0x5000c,
983 .mnd_width = 0,
996 .halt_reg = 0x75034,
999 .enable_reg = 0x75034,
1000 .enable_mask = BIT(0),
1013 .halt_reg = 0xf03c,
1016 .enable_reg = 0xf03c,
1017 .enable_mask = BIT(0),
1030 .halt_reg = 0x7106c,
1033 .enable_reg = 0x7106c,
1034 .enable_mask = BIT(0),
1043 .halt_reg = 0x48004,
1046 .enable_reg = 0x52004,
1056 .halt_reg = 0x4401c,
1059 .enable_reg = 0x4401c,
1060 .enable_mask = BIT(0),
1069 .halt_reg = 0x17004,
1072 .enable_reg = 0x52004,
1082 .halt_reg = 0x19008,
1085 .enable_reg = 0x19008,
1086 .enable_mask = BIT(0),
1100 .halt_reg = 0x19004,
1103 .enable_reg = 0x19004,
1104 .enable_mask = BIT(0),
1118 .halt_reg = 0x1b008,
1121 .enable_reg = 0x1b008,
1122 .enable_mask = BIT(0),
1136 .halt_reg = 0x1b004,
1139 .enable_reg = 0x1b004,
1140 .enable_mask = BIT(0),
1154 .halt_reg = 0x1d008,
1157 .enable_reg = 0x1d008,
1158 .enable_mask = BIT(0),
1172 .halt_reg = 0x1d004,
1175 .enable_reg = 0x1d004,
1176 .enable_mask = BIT(0),
1190 .halt_reg = 0x1f008,
1193 .enable_reg = 0x1f008,
1194 .enable_mask = BIT(0),
1208 .halt_reg = 0x1f004,
1211 .enable_reg = 0x1f004,
1212 .enable_mask = BIT(0),
1226 .halt_reg = 0x1a004,
1229 .enable_reg = 0x1a004,
1230 .enable_mask = BIT(0),
1244 .halt_reg = 0x1c004,
1247 .enable_reg = 0x1c004,
1248 .enable_mask = BIT(0),
1262 .halt_reg = 0x25004,
1265 .enable_reg = 0x52004,
1275 .halt_reg = 0x26008,
1278 .enable_reg = 0x26008,
1279 .enable_mask = BIT(0),
1293 .halt_reg = 0x26004,
1296 .enable_reg = 0x26004,
1297 .enable_mask = BIT(0),
1311 .halt_reg = 0x28008,
1314 .enable_reg = 0x28008,
1315 .enable_mask = BIT(0),
1329 .halt_reg = 0x28004,
1332 .enable_reg = 0x28004,
1333 .enable_mask = BIT(0),
1347 .halt_reg = 0x2a008,
1350 .enable_reg = 0x2a008,
1351 .enable_mask = BIT(0),
1365 .halt_reg = 0x2a004,
1368 .enable_reg = 0x2a004,
1369 .enable_mask = BIT(0),
1383 .halt_reg = 0x2c008,
1386 .enable_reg = 0x2c008,
1387 .enable_mask = BIT(0),
1401 .halt_reg = 0x2c004,
1404 .enable_reg = 0x2c004,
1405 .enable_mask = BIT(0),
1419 .halt_reg = 0x27004,
1422 .enable_reg = 0x27004,
1423 .enable_mask = BIT(0),
1437 .halt_reg = 0x29004,
1440 .enable_reg = 0x29004,
1441 .enable_mask = BIT(0),
1455 .halt_reg = 0x38004,
1458 .enable_reg = 0x52004,
1468 .halt_reg = 0x5058,
1471 .enable_reg = 0x5058,
1472 .enable_mask = BIT(0),
1485 .halt_reg = 0x5018,
1488 .enable_reg = 0x5018,
1489 .enable_mask = BIT(0),
1502 .halt_reg = 0x84004,
1504 .enable_reg = 0x84004,
1505 .enable_mask = BIT(0),
1514 .halt_reg = 0x64000,
1517 .enable_reg = 0x64000,
1518 .enable_mask = BIT(0),
1532 .halt_reg = 0x65000,
1535 .enable_reg = 0x65000,
1536 .enable_mask = BIT(0),
1550 .halt_reg = 0x66000,
1553 .enable_reg = 0x66000,
1554 .enable_mask = BIT(0),
1568 .halt_reg = 0x71010,
1571 .enable_reg = 0x71010,
1572 .enable_mask = BIT(0),
1581 .halt_reg = 0x71004,
1584 .enable_reg = 0x71004,
1585 .enable_mask = BIT(0),
1595 .halt_reg = 0x5200c,
1598 .enable_reg = 0x5200c,
1612 .halt_reg = 0x5200c,
1615 .enable_reg = 0x5200c,
1629 .halt_reg = 0x4808c,
1632 .enable_reg = 0x4808c,
1633 .enable_mask = BIT(0),
1643 .halt_reg = 0x48008,
1646 .enable_reg = 0x48008,
1647 .enable_mask = BIT(0),
1661 .halt_reg = 0x5200c,
1664 .enable_reg = 0x5200c,
1678 .halt_reg = 0x5200c,
1681 .enable_reg = 0x5200c,
1682 .enable_mask = BIT(0),
1695 .halt_reg = 0x9004,
1698 .enable_reg = 0x9004,
1699 .enable_mask = BIT(0),
1714 .halt_reg = 0x9000,
1717 .enable_reg = 0x9000,
1718 .enable_mask = BIT(0),
1727 .halt_reg = 0x8a000,
1729 .enable_reg = 0x8a000,
1730 .enable_mask = BIT(0),
1739 .halt_reg = 0x8a004,
1741 .hwcg_reg = 0x8a004,
1744 .enable_reg = 0x8a004,
1745 .enable_mask = BIT(0),
1754 .halt_reg = 0x8a040,
1756 .enable_reg = 0x8a040,
1757 .enable_mask = BIT(0),
1766 .halt_reg = 0x8a03c,
1768 .enable_reg = 0x8a03c,
1769 .enable_mask = BIT(0),
1778 .halt_reg = 0x3300c,
1781 .enable_reg = 0x3300c,
1782 .enable_mask = BIT(0),
1796 .halt_reg = 0x33004,
1799 .enable_reg = 0x33004,
1800 .enable_mask = BIT(0),
1809 .halt_reg = 0x34004,
1812 .enable_reg = 0x52004,
1822 .halt_reg = 0x4d004,
1825 .enable_reg = 0x4d004,
1826 .enable_mask = BIT(0),
1835 .halt_reg = 0x4d008,
1838 .enable_reg = 0x4d008,
1839 .enable_mask = BIT(0),
1853 .halt_reg = 0x88018,
1856 .enable_reg = 0x88018,
1857 .enable_mask = BIT(0),
1866 .halt_reg = 0x88014,
1869 .enable_reg = 0x88014,
1870 .enable_mask = BIT(0),
1879 .halt_reg = 0x16008,
1882 .enable_reg = 0x16008,
1883 .enable_mask = BIT(0),
1892 .halt_reg = 0x16004,
1895 .enable_reg = 0x16004,
1896 .enable_mask = BIT(0),
1910 .halt_reg = 0x1600c,
1913 .enable_reg = 0x1600c,
1914 .enable_mask = BIT(0),
1928 .halt_reg = 0x14008,
1931 .enable_reg = 0x14008,
1932 .enable_mask = BIT(0),
1941 .halt_reg = 0x14004,
1944 .enable_reg = 0x14004,
1945 .enable_mask = BIT(0),
1959 .halt_reg = 0x7500c,
1962 .enable_reg = 0x7500c,
1963 .enable_mask = BIT(0),
1972 .halt_reg = 0x75008,
1975 .enable_reg = 0x75008,
1976 .enable_mask = BIT(0),
1990 .halt_reg = 0x88008,
1993 .enable_reg = 0x88008,
1994 .enable_mask = BIT(0),
2003 .halt_reg = 0x7600c,
2006 .enable_reg = 0x7600c,
2007 .enable_mask = BIT(0),
2021 .halt_reg = 0x76040,
2024 .enable_reg = 0x76040,
2025 .enable_mask = BIT(0),
2039 .halt_reg = 0x75014,
2042 .enable_reg = 0x75014,
2043 .enable_mask = BIT(0),
2052 .halt_reg = 0x7605c,
2055 .enable_reg = 0x7605c,
2056 .enable_mask = BIT(0),
2065 .halt_reg = 0x75010,
2068 .enable_reg = 0x75010,
2069 .enable_mask = BIT(0),
2078 .halt_reg = 0x76008,
2081 .enable_reg = 0x76008,
2082 .enable_mask = BIT(0),
2096 .halt_reg = 0x2f004,
2099 .enable_reg = 0x2f004,
2100 .enable_mask = BIT(0),
2114 .halt_reg = 0x2f00c,
2117 .enable_reg = 0x2f00c,
2118 .enable_mask = BIT(0),
2132 .halt_reg = 0x2f008,
2135 .enable_reg = 0x2f008,
2136 .enable_mask = BIT(0),
2145 .halt_reg = 0xf008,
2148 .enable_reg = 0xf008,
2149 .enable_mask = BIT(0),
2163 .halt_reg = 0xf010,
2166 .enable_reg = 0xf010,
2167 .enable_mask = BIT(0),
2181 .halt_reg = 0xf00c,
2184 .enable_reg = 0xf00c,
2185 .enable_mask = BIT(0),
2194 .halt_reg = 0x8800c,
2197 .enable_reg = 0x8800c,
2198 .enable_mask = BIT(0),
2207 .halt_reg = 0x50000,
2210 .enable_reg = 0x50000,
2211 .enable_mask = BIT(0),
2225 .halt_reg = 0x50004,
2228 .enable_reg = 0x50004,
2229 .enable_mask = BIT(0),
2238 .halt_reg = 0x6a004,
2241 .enable_reg = 0x6a004,
2242 .enable_mask = BIT(0),
2251 .gdscr = 0x75004,
2252 .gds_hw_ctrl = 0x0,
2261 .gdscr = 0xf004,
2262 .gds_hw_ctrl = 0x0,
2271 .gdscr = 0x6b004,
2272 .gds_hw_ctrl = 0x0,
2421 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2422 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2423 [GCC_UFS_BCR] = { 0x75000 },
2424 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
2425 [GCC_USB3_PHY_BCR] = { 0x50020 },
2426 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
2427 [GCC_USB_20_BCR] = { 0x2f000 },
2428 [GCC_USB_30_BCR] = { 0xf000 },
2429 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2430 [GCC_MSS_RESTART] = { 0x79000 },
2437 .max_register = 0x94000,
2473 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_sdm660_probe()