Lines Matching +full:0 +full:x12010
113 .offset = 0x0,
116 .enable_reg = 0x52028,
117 .enable_mask = BIT(0),
128 { 0x1, 2 },
133 .offset = 0x0,
150 .offset = 0x2000,
153 .enable_reg = 0x52028,
165 .offset = 0x76000,
168 .enable_reg = 0x52028,
180 .offset = 0x1a000,
183 .enable_reg = 0x52028,
195 .offset = 0x1b000,
198 .enable_reg = 0x52028,
210 .offset = 0x1c000,
213 .enable_reg = 0x52028,
228 { P_BI_TCXO, 0 },
240 { P_BI_TCXO, 0 },
250 { P_BI_TCXO, 0 },
264 { P_BI_TCXO, 0 },
272 { P_BI_TCXO, 0 },
286 { P_BI_TCXO, 0 },
300 { P_BI_TCXO, 0 },
312 { P_BI_TCXO, 0 },
324 { P_BI_TCXO, 0 },
338 { P_BI_TCXO, 0 },
352 { P_BI_TCXO, 0 },
368 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
378 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
388 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
398 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
408 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
418 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
428 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
438 { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
448 .reg = 0xf060,
449 .shift = 0,
463 .reg = 0x10060,
464 .shift = 0,
478 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 },
488 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 },
498 { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
510 { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
522 { P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC, 0 },
532 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
542 { P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
552 .reg = 0xb80dc,
553 .shift = 0,
567 { P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
577 { P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
587 { P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
597 { P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
607 { P_GCC_USB4_PHY_DP_GMUX_CLK_SRC, 0 },
617 { P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
627 { P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
637 .reg = 0x2a0dc,
638 .shift = 0,
652 { P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
662 { P_QUSB4PHY_GCC_USB4_RX0_CLK, 0 },
672 { P_QUSB4PHY_GCC_USB4_RX1_CLK, 0 },
682 { P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
692 .reg = 0x9d05c,
706 .reg = 0x9e05c,
720 .reg = 0xa005c,
734 .reg = 0xa205c,
748 .reg = 0x6b05c,
762 .reg = 0x75058,
763 .shift = 0,
777 .reg = 0x750c8,
778 .shift = 0,
792 .reg = 0x75048,
793 .shift = 0,
807 .reg = 0x77058,
808 .shift = 0,
822 .reg = 0x770c8,
823 .shift = 0,
837 .reg = 0x77048,
838 .shift = 0,
852 .reg = 0xf064,
853 .shift = 0,
867 .reg = 0x10064,
868 .shift = 0,
882 .reg = 0xab060,
883 .shift = 0,
897 .reg = 0xab068,
898 .shift = 0,
912 .reg = 0xb8050,
913 .shift = 0,
927 .reg = 0xb80b0,
928 .shift = 0,
942 .reg = 0xb80e0,
943 .shift = 0,
957 .reg = 0xb8090,
958 .shift = 0,
972 .reg = 0xb809c,
973 .shift = 0,
987 .reg = 0xb80c0,
988 .shift = 0,
1002 .reg = 0x2a050,
1003 .shift = 0,
1017 .reg = 0x2a0b0,
1018 .shift = 0,
1032 .reg = 0x2a0e0,
1033 .shift = 0,
1047 .reg = 0x2a090,
1048 .shift = 0,
1062 .reg = 0x2a09c,
1063 .shift = 0,
1077 .reg = 0x2a0c0,
1078 .shift = 0,
1092 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1093 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1094 F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
1099 .cmd_rcgr = 0xaa020,
1100 .mnd_width = 0,
1113 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1114 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1115 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
1120 .cmd_rcgr = 0xaa040,
1134 .cmd_rcgr = 0xba020,
1135 .mnd_width = 0,
1148 .cmd_rcgr = 0xba040,
1162 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1163 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1164 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1169 .cmd_rcgr = 0x64004,
1183 .cmd_rcgr = 0x65004,
1197 .cmd_rcgr = 0x66004,
1211 .cmd_rcgr = 0xc2004,
1225 .cmd_rcgr = 0xc3004,
1239 F(9600000, P_BI_TCXO, 2, 0, 0),
1240 F(19200000, P_BI_TCXO, 1, 0, 0),
1245 .cmd_rcgr = 0xa4054,
1259 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1264 .cmd_rcgr = 0xa403c,
1265 .mnd_width = 0,
1278 F(19200000, P_BI_TCXO, 1, 0, 0),
1283 .cmd_rcgr = 0x8d054,
1297 .cmd_rcgr = 0x8d03c,
1298 .mnd_width = 0,
1311 .cmd_rcgr = 0x9d064,
1325 .cmd_rcgr = 0x9d044,
1326 .mnd_width = 0,
1339 .cmd_rcgr = 0x9e064,
1353 .cmd_rcgr = 0x9e044,
1354 .mnd_width = 0,
1367 .cmd_rcgr = 0xa0064,
1381 .cmd_rcgr = 0xa0044,
1382 .mnd_width = 0,
1395 .cmd_rcgr = 0xa2064,
1409 .cmd_rcgr = 0xa2044,
1410 .mnd_width = 0,
1423 .cmd_rcgr = 0x6b064,
1437 .cmd_rcgr = 0x6b044,
1438 .mnd_width = 0,
1451 .cmd_rcgr = 0xae00c,
1452 .mnd_width = 0,
1465 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1470 .cmd_rcgr = 0x33010,
1471 .mnd_width = 0,
1486 F(19200000, P_BI_TCXO, 1, 0, 0),
1491 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1494 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1507 .cmd_rcgr = 0x17148,
1524 .cmd_rcgr = 0x17278,
1541 .cmd_rcgr = 0x173a8,
1558 .cmd_rcgr = 0x174d8,
1575 .cmd_rcgr = 0x17608,
1592 .cmd_rcgr = 0x17738,
1603 F(19200000, P_BI_TCXO, 1, 0, 0),
1608 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1611 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1624 .cmd_rcgr = 0x17868,
1641 .cmd_rcgr = 0x17998,
1658 .cmd_rcgr = 0x18148,
1675 .cmd_rcgr = 0x18278,
1692 .cmd_rcgr = 0x183a8,
1709 .cmd_rcgr = 0x184d8,
1726 .cmd_rcgr = 0x18608,
1743 .cmd_rcgr = 0x18738,
1760 .cmd_rcgr = 0x18868,
1777 .cmd_rcgr = 0x18998,
1794 .cmd_rcgr = 0x1e148,
1811 .cmd_rcgr = 0x1e278,
1828 .cmd_rcgr = 0x1e3a8,
1845 .cmd_rcgr = 0x1e4d8,
1862 .cmd_rcgr = 0x1e608,
1879 .cmd_rcgr = 0x1e738,
1896 .cmd_rcgr = 0x1e868,
1913 .cmd_rcgr = 0x1e998,
1923 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1924 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1925 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1926 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1931 .cmd_rcgr = 0x1400c,
1946 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1947 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1952 .cmd_rcgr = 0x1600c,
1966 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1967 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1968 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1969 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1974 .cmd_rcgr = 0x75024,
1988 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1989 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1990 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1995 .cmd_rcgr = 0x7506c,
1996 .mnd_width = 0,
2009 .cmd_rcgr = 0x750a0,
2010 .mnd_width = 0,
2023 .cmd_rcgr = 0x75084,
2024 .mnd_width = 0,
2037 .cmd_rcgr = 0x77024,
2051 .cmd_rcgr = 0x7706c,
2052 .mnd_width = 0,
2065 .cmd_rcgr = 0x770a0,
2066 .mnd_width = 0,
2079 .cmd_rcgr = 0x77084,
2080 .mnd_width = 0,
2093 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
2094 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
2095 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
2096 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
2101 .cmd_rcgr = 0xab020,
2115 .cmd_rcgr = 0xab038,
2116 .mnd_width = 0,
2129 .cmd_rcgr = 0xf020,
2143 .cmd_rcgr = 0xf038,
2144 .mnd_width = 0,
2157 .cmd_rcgr = 0x10020,
2171 .cmd_rcgr = 0x10038,
2172 .mnd_width = 0,
2185 .cmd_rcgr = 0xab06c,
2186 .mnd_width = 0,
2199 .cmd_rcgr = 0xf068,
2200 .mnd_width = 0,
2213 .cmd_rcgr = 0x10068,
2214 .mnd_width = 0,
2227 F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
2228 F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2229 F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2234 .cmd_rcgr = 0xb8018,
2248 F(19200000, P_BI_TCXO, 1, 0, 0),
2249 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
2250 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
2255 .cmd_rcgr = 0xb80c4,
2256 .mnd_width = 0,
2269 .cmd_rcgr = 0xb8070,
2270 .mnd_width = 0,
2283 F(19200000, P_BI_TCXO, 1, 0, 0),
2284 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
2289 .cmd_rcgr = 0xb8054,
2290 .mnd_width = 0,
2303 .cmd_rcgr = 0x2a018,
2317 .cmd_rcgr = 0x2a0c4,
2318 .mnd_width = 0,
2331 .cmd_rcgr = 0x2a070,
2332 .mnd_width = 0,
2345 .cmd_rcgr = 0x2a054,
2346 .mnd_width = 0,
2359 .reg = 0x9d060,
2360 .shift = 0,
2374 .reg = 0x9e060,
2375 .shift = 0,
2389 .reg = 0xa0060,
2390 .shift = 0,
2404 .reg = 0xa2060,
2405 .shift = 0,
2419 .reg = 0x6b060,
2420 .shift = 0,
2434 .reg = 0x17ac8,
2435 .shift = 0,
2449 .reg = 0x18ac8,
2450 .shift = 0,
2464 .reg = 0x1eac8,
2465 .shift = 0,
2479 .reg = 0xab050,
2480 .shift = 0,
2494 .reg = 0xf050,
2495 .shift = 0,
2509 .reg = 0x10050,
2510 .shift = 0,
2524 .halt_reg = 0xa41a8,
2526 .hwcg_reg = 0xa41a8,
2529 .enable_reg = 0x52018,
2539 .halt_reg = 0x8d07c,
2541 .hwcg_reg = 0x8d07c,
2544 .enable_reg = 0x52018,
2554 .halt_reg = 0x6b1b8,
2556 .hwcg_reg = 0x6b1b8,
2559 .enable_reg = 0x52000,
2569 .halt_reg = 0xbf13c,
2571 .hwcg_reg = 0xbf13c,
2574 .enable_reg = 0x52018,
2584 .halt_reg = 0x750cc,
2586 .hwcg_reg = 0x750cc,
2589 .enable_reg = 0x750cc,
2590 .enable_mask = BIT(0),
2604 .halt_reg = 0x750cc,
2606 .hwcg_reg = 0x750cc,
2609 .enable_reg = 0x750cc,
2624 .halt_reg = 0x770cc,
2626 .hwcg_reg = 0x770cc,
2629 .enable_reg = 0x770cc,
2630 .enable_mask = BIT(0),
2644 .halt_reg = 0x770cc,
2646 .hwcg_reg = 0x770cc,
2649 .enable_reg = 0x770cc,
2664 .halt_reg = 0xab084,
2666 .hwcg_reg = 0xab084,
2669 .enable_reg = 0xab084,
2670 .enable_mask = BIT(0),
2684 .halt_reg = 0xf080,
2686 .hwcg_reg = 0xf080,
2689 .enable_reg = 0xf080,
2690 .enable_mask = BIT(0),
2704 .halt_reg = 0x10080,
2706 .hwcg_reg = 0x10080,
2709 .enable_reg = 0x10080,
2710 .enable_mask = BIT(0),
2724 .halt_reg = 0xb80e4,
2726 .hwcg_reg = 0xb80e4,
2729 .enable_reg = 0xb80e4,
2730 .enable_mask = BIT(0),
2744 .halt_reg = 0x2a0e4,
2746 .hwcg_reg = 0x2a0e4,
2749 .enable_reg = 0x2a0e4,
2750 .enable_mask = BIT(0),
2764 .halt_reg = 0x5d024,
2766 .hwcg_reg = 0x5d024,
2769 .enable_reg = 0x5d024,
2770 .enable_mask = BIT(0),
2779 .halt_reg = 0x5d020,
2781 .hwcg_reg = 0x5d020,
2784 .enable_reg = 0x5d020,
2785 .enable_mask = BIT(0),
2794 .halt_reg = 0x5d01c,
2796 .hwcg_reg = 0x5d01c,
2799 .enable_reg = 0x5d01c,
2800 .enable_mask = BIT(0),
2809 .halt_reg = 0x6a004,
2811 .hwcg_reg = 0x6a004,
2814 .enable_reg = 0x6a004,
2815 .enable_mask = BIT(0),
2824 .halt_reg = 0x6a008,
2826 .hwcg_reg = 0x6a008,
2829 .enable_reg = 0x6a008,
2830 .enable_mask = BIT(0),
2839 .halt_reg = 0x38004,
2841 .hwcg_reg = 0x38004,
2844 .enable_reg = 0x52000,
2854 .halt_reg = 0x26010,
2856 .hwcg_reg = 0x26010,
2859 .enable_reg = 0x26010,
2860 .enable_mask = BIT(0),
2869 .halt_reg = 0x26014,
2871 .hwcg_reg = 0x26014,
2874 .enable_reg = 0x26014,
2875 .enable_mask = BIT(0),
2884 .halt_reg = 0x2601c,
2886 .hwcg_reg = 0x2601c,
2889 .enable_reg = 0x2601c,
2890 .enable_mask = BIT(0),
2899 .halt_reg = 0x26018,
2901 .hwcg_reg = 0x26018,
2904 .enable_reg = 0x26018,
2905 .enable_mask = BIT(0),
2914 .halt_reg = 0x26024,
2917 .enable_reg = 0x26024,
2918 .enable_mask = BIT(0),
2927 .halt_reg = 0xab088,
2929 .hwcg_reg = 0xab088,
2932 .enable_reg = 0xab088,
2933 .enable_mask = BIT(0),
2947 .halt_reg = 0xf084,
2949 .hwcg_reg = 0xf084,
2952 .enable_reg = 0xf084,
2953 .enable_mask = BIT(0),
2967 .halt_reg = 0x10084,
2969 .hwcg_reg = 0x10084,
2972 .enable_reg = 0x10084,
2973 .enable_mask = BIT(0),
2987 .halt_reg = 0xa4074,
2990 .enable_reg = 0x52020,
3000 .halt_reg = 0x8d074,
3003 .enable_reg = 0x52020,
3013 .halt_reg = 0x6b084,
3015 .hwcg_reg = 0x6b084,
3018 .enable_reg = 0x52020,
3028 .halt_reg = 0x7115c,
3030 .hwcg_reg = 0x7115c,
3033 .enable_reg = 0x7115c,
3034 .enable_mask = BIT(0),
3043 .halt_reg = 0xa602c,
3045 .hwcg_reg = 0xa602c,
3048 .enable_reg = 0x52000,
3058 .halt_reg = 0xbb010,
3060 .hwcg_reg = 0xbb010,
3063 .enable_reg = 0xbb010,
3064 .enable_mask = BIT(0),
3073 .halt_reg = 0xbb018,
3075 .hwcg_reg = 0xbb018,
3078 .enable_reg = 0xbb018,
3079 .enable_mask = BIT(0),
3088 .halt_reg = 0xbb024,
3090 .hwcg_reg = 0xbb024,
3093 .enable_reg = 0xbb024,
3094 .enable_mask = BIT(0),
3103 .halt_reg = 0xbb020,
3105 .hwcg_reg = 0xbb020,
3108 .enable_reg = 0xbb020,
3109 .enable_mask = BIT(0),
3118 .halt_reg = 0x27010,
3120 .hwcg_reg = 0x27010,
3123 .enable_reg = 0x27010,
3124 .enable_mask = BIT(0),
3133 .halt_reg = 0x27018,
3135 .hwcg_reg = 0x27018,
3138 .enable_reg = 0x27018,
3139 .enable_mask = BIT(0),
3148 .halt_reg = 0x27024,
3150 .hwcg_reg = 0x27024,
3153 .enable_reg = 0x27024,
3154 .enable_mask = BIT(0),
3163 .halt_reg = 0x27020,
3165 .hwcg_reg = 0x27020,
3168 .enable_reg = 0x27020,
3169 .enable_mask = BIT(0),
3178 .halt_reg = 0xaa010,
3180 .hwcg_reg = 0xaa010,
3183 .enable_reg = 0xaa010,
3184 .enable_mask = BIT(0),
3193 .halt_reg = 0xaa01c,
3196 .enable_reg = 0xaa01c,
3197 .enable_mask = BIT(0),
3211 .halt_reg = 0xaa038,
3214 .enable_reg = 0xaa038,
3215 .enable_mask = BIT(0),
3229 .halt_reg = 0xaa018,
3231 .hwcg_reg = 0xaa018,
3234 .enable_reg = 0xaa018,
3235 .enable_mask = BIT(0),
3244 .halt_reg = 0xba010,
3246 .hwcg_reg = 0xba010,
3249 .enable_reg = 0xba010,
3250 .enable_mask = BIT(0),
3259 .halt_reg = 0xba01c,
3262 .enable_reg = 0xba01c,
3263 .enable_mask = BIT(0),
3277 .halt_reg = 0xba038,
3280 .enable_reg = 0xba038,
3281 .enable_mask = BIT(0),
3295 .halt_reg = 0xba018,
3297 .hwcg_reg = 0xba018,
3300 .enable_reg = 0xba018,
3301 .enable_mask = BIT(0),
3310 .halt_reg = 0x64000,
3313 .enable_reg = 0x64000,
3314 .enable_mask = BIT(0),
3328 .halt_reg = 0x65000,
3331 .enable_reg = 0x65000,
3332 .enable_mask = BIT(0),
3346 .halt_reg = 0x66000,
3349 .enable_reg = 0x66000,
3350 .enable_mask = BIT(0),
3364 .halt_reg = 0xc2000,
3367 .enable_reg = 0xc2000,
3368 .enable_mask = BIT(0),
3382 .halt_reg = 0xc3000,
3385 .enable_reg = 0xc3000,
3386 .enable_mask = BIT(0),
3402 .enable_reg = 0x52000,
3419 .enable_reg = 0x52000,
3434 .halt_reg = 0x8c014,
3437 .enable_reg = 0x8c014,
3438 .enable_mask = BIT(0),
3447 .halt_reg = 0x71010,
3449 .hwcg_reg = 0x71010,
3452 .enable_reg = 0x71010,
3453 .enable_mask = BIT(0),
3462 .halt_reg = 0x71020,
3465 .enable_reg = 0x71020,
3466 .enable_mask = BIT(0),
3475 .halt_reg = 0x71008,
3477 .hwcg_reg = 0x71008,
3480 .enable_reg = 0x71008,
3481 .enable_mask = BIT(0),
3490 .halt_reg = 0x71018,
3492 .hwcg_reg = 0x71018,
3495 .enable_reg = 0x71018,
3496 .enable_mask = BIT(0),
3505 .halt_reg = 0xa4038,
3508 .enable_reg = 0x52018,
3523 .halt_reg = 0x8d038,
3526 .enable_reg = 0x52000,
3541 .halt_reg = 0x9d040,
3544 .enable_reg = 0x52010,
3559 .halt_reg = 0x9e040,
3562 .enable_reg = 0x52010,
3577 .halt_reg = 0xa0040,
3580 .enable_reg = 0x52010,
3595 .halt_reg = 0xa2040,
3598 .enable_reg = 0x52018,
3613 .halt_reg = 0x6b040,
3616 .enable_reg = 0x52000,
3631 .halt_reg = 0xa4028,
3634 .enable_reg = 0x52018,
3649 .halt_reg = 0xa4024,
3651 .hwcg_reg = 0xa4024,
3654 .enable_reg = 0x52018,
3664 .halt_reg = 0xa401c,
3666 .hwcg_reg = 0xa401c,
3669 .enable_reg = 0x52018,
3679 .halt_reg = 0xa4030,
3682 .enable_reg = 0x52018,
3697 .halt_reg = 0xa4014,
3699 .hwcg_reg = 0xa4014,
3702 .enable_reg = 0x52018,
3712 .halt_reg = 0xa4010,
3715 .enable_reg = 0x52018,
3725 .halt_reg = 0x8d028,
3728 .enable_reg = 0x52000,
3743 .halt_reg = 0x8d024,
3745 .hwcg_reg = 0x8d024,
3748 .enable_reg = 0x52000,
3758 .halt_reg = 0x8d01c,
3760 .hwcg_reg = 0x8d01c,
3763 .enable_reg = 0x52000,
3773 .halt_reg = 0x8d030,
3776 .enable_reg = 0x52000,
3791 .halt_reg = 0x8d014,
3793 .hwcg_reg = 0x8d014,
3796 .enable_reg = 0x52000,
3806 .halt_reg = 0x8d010,
3809 .enable_reg = 0x52000,
3819 .halt_reg = 0x8c034,
3822 .enable_reg = 0x8c034,
3823 .enable_mask = BIT(0),
3832 .halt_reg = 0x9d028,
3835 .enable_reg = 0x52010,
3850 .halt_reg = 0x9d024,
3852 .hwcg_reg = 0x9d024,
3855 .enable_reg = 0x52010,
3865 .halt_reg = 0x9d01c,
3867 .hwcg_reg = 0x9d01c,
3870 .enable_reg = 0x52010,
3880 .halt_reg = 0x9d030,
3883 .enable_reg = 0x52010,
3898 .halt_reg = 0x9d038,
3901 .enable_reg = 0x52018,
3916 .halt_reg = 0x9d014,
3918 .hwcg_reg = 0x9d014,
3921 .enable_reg = 0x52010,
3931 .halt_reg = 0x9d010,
3934 .enable_reg = 0x52018,
3944 .halt_reg = 0x9e028,
3947 .enable_reg = 0x52010,
3962 .halt_reg = 0x9e024,
3964 .hwcg_reg = 0x9e024,
3967 .enable_reg = 0x52010,
3977 .halt_reg = 0x9e01c,
3979 .hwcg_reg = 0x9e01c,
3982 .enable_reg = 0x52010,
3992 .halt_reg = 0x9e030,
3995 .enable_reg = 0x52010,
4010 .halt_reg = 0x9e038,
4013 .enable_reg = 0x52018,
4028 .halt_reg = 0x9e014,
4030 .hwcg_reg = 0x9e014,
4033 .enable_reg = 0x52010,
4043 .halt_reg = 0x9e010,
4046 .enable_reg = 0x52010,
4056 .halt_reg = 0x8c038,
4059 .enable_reg = 0x8c038,
4060 .enable_mask = BIT(0),
4069 .halt_reg = 0xa0028,
4072 .enable_reg = 0x52010,
4087 .halt_reg = 0xa0024,
4089 .hwcg_reg = 0xa0024,
4092 .enable_reg = 0x52010,
4102 .halt_reg = 0xa001c,
4104 .hwcg_reg = 0xa001c,
4107 .enable_reg = 0x52010,
4117 .halt_reg = 0xa0030,
4120 .enable_reg = 0x52010,
4135 .halt_reg = 0xa0038,
4138 .enable_reg = 0x52018,
4153 .halt_reg = 0xa0014,
4155 .hwcg_reg = 0xa0014,
4158 .enable_reg = 0x52010,
4168 .halt_reg = 0xa0010,
4171 .enable_reg = 0x52010,
4181 .halt_reg = 0xa2028,
4184 .enable_reg = 0x52018,
4199 .halt_reg = 0xa2024,
4201 .hwcg_reg = 0xa2024,
4204 .enable_reg = 0x52018,
4214 .halt_reg = 0xa201c,
4216 .hwcg_reg = 0xa201c,
4219 .enable_reg = 0x52018,
4220 .enable_mask = BIT(0),
4229 .halt_reg = 0xa2030,
4232 .enable_reg = 0x52018,
4247 .halt_reg = 0xa2038,
4250 .enable_reg = 0x52018,
4265 .halt_reg = 0xa2014,
4267 .hwcg_reg = 0xa2014,
4270 .enable_reg = 0x52010,
4280 .halt_reg = 0xa2010,
4283 .enable_reg = 0x52010,
4293 .halt_reg = 0x6b028,
4296 .enable_reg = 0x52008,
4311 .halt_reg = 0x6b024,
4313 .hwcg_reg = 0x6b024,
4316 .enable_reg = 0x52008,
4326 .halt_reg = 0x8c030,
4329 .enable_reg = 0x8c030,
4330 .enable_mask = BIT(0),
4339 .halt_reg = 0x6b01c,
4341 .hwcg_reg = 0x6b01c,
4344 .enable_reg = 0x52008,
4354 .halt_reg = 0x6b030,
4357 .enable_reg = 0x52008,
4372 .halt_reg = 0x6b038,
4375 .enable_reg = 0x52018,
4390 .halt_reg = 0x6b014,
4392 .hwcg_reg = 0x6b014,
4395 .enable_reg = 0x52008,
4396 .enable_mask = BIT(0),
4405 .halt_reg = 0x6b010,
4408 .enable_reg = 0x52008,
4418 .halt_reg = 0xae008,
4420 .hwcg_reg = 0xae008,
4423 .enable_reg = 0x52020,
4433 .halt_reg = 0xae004,
4436 .enable_reg = 0x52020,
4451 .halt_reg = 0xa6028,
4454 .enable_reg = 0x52020,
4464 .halt_reg = 0x3300c,
4467 .enable_reg = 0x3300c,
4468 .enable_mask = BIT(0),
4482 .halt_reg = 0x33004,
4484 .hwcg_reg = 0x33004,
4487 .enable_reg = 0x33004,
4488 .enable_mask = BIT(0),
4497 .halt_reg = 0x33008,
4500 .enable_reg = 0x33008,
4501 .enable_mask = BIT(0),
4510 .halt_reg = 0x26008,
4512 .hwcg_reg = 0x26008,
4515 .enable_reg = 0x26008,
4516 .enable_mask = BIT(0),
4525 .halt_reg = 0x2600c,
4527 .hwcg_reg = 0x2600c,
4530 .enable_reg = 0x2600c,
4531 .enable_mask = BIT(0),
4540 .halt_reg = 0xbb008,
4542 .hwcg_reg = 0xbb008,
4545 .enable_reg = 0xbb008,
4546 .enable_mask = BIT(0),
4555 .halt_reg = 0xbb00c,
4557 .hwcg_reg = 0xbb00c,
4560 .enable_reg = 0xbb00c,
4561 .enable_mask = BIT(0),
4570 .halt_reg = 0x27008,
4572 .hwcg_reg = 0x27008,
4575 .enable_reg = 0x27008,
4576 .enable_mask = BIT(0),
4585 .halt_reg = 0x2700c,
4587 .hwcg_reg = 0x2700c,
4590 .enable_reg = 0x2700c,
4591 .enable_mask = BIT(0),
4600 .halt_reg = 0x28008,
4602 .hwcg_reg = 0x28008,
4605 .enable_reg = 0x28008,
4606 .enable_mask = BIT(0),
4615 .halt_reg = 0x2800c,
4617 .hwcg_reg = 0x2800c,
4620 .enable_reg = 0x2800c,
4621 .enable_mask = BIT(0),
4630 .halt_reg = 0x17014,
4633 .enable_reg = 0x52008,
4643 .halt_reg = 0x1700c,
4646 .enable_reg = 0x52008,
4656 .halt_reg = 0x17ac4,
4659 .enable_reg = 0x52020,
4660 .enable_mask = BIT(0),
4674 .halt_reg = 0x17144,
4677 .enable_reg = 0x52008,
4692 .halt_reg = 0x17274,
4695 .enable_reg = 0x52008,
4710 .halt_reg = 0x173a4,
4713 .enable_reg = 0x52008,
4728 .halt_reg = 0x174d4,
4731 .enable_reg = 0x52008,
4746 .halt_reg = 0x17604,
4749 .enable_reg = 0x52008,
4764 .halt_reg = 0x17734,
4767 .enable_reg = 0x52008,
4782 .halt_reg = 0x17864,
4785 .enable_reg = 0x52008,
4800 .halt_reg = 0x17994,
4803 .enable_reg = 0x52008,
4818 .halt_reg = 0x18014,
4821 .enable_reg = 0x52008,
4831 .halt_reg = 0x1800c,
4834 .enable_reg = 0x52008,
4844 .halt_reg = 0x18ac4,
4847 .enable_reg = 0x52020,
4862 .halt_reg = 0x18144,
4865 .enable_reg = 0x52008,
4880 .halt_reg = 0x18274,
4883 .enable_reg = 0x52008,
4898 .halt_reg = 0x183a4,
4901 .enable_reg = 0x52008,
4916 .halt_reg = 0x184d4,
4919 .enable_reg = 0x52008,
4934 .halt_reg = 0x18604,
4937 .enable_reg = 0x52008,
4952 .halt_reg = 0x18734,
4955 .enable_reg = 0x52008,
4970 .halt_reg = 0x18864,
4973 .enable_reg = 0x52018,
4988 .halt_reg = 0x18994,
4991 .enable_reg = 0x52018,
5006 .halt_reg = 0x1e014,
5009 .enable_reg = 0x52010,
5019 .halt_reg = 0x1e00c,
5022 .enable_reg = 0x52010,
5023 .enable_mask = BIT(0),
5032 .halt_reg = 0x1eac4,
5035 .enable_reg = 0x52020,
5050 .halt_reg = 0x1e144,
5053 .enable_reg = 0x52010,
5068 .halt_reg = 0x1e274,
5071 .enable_reg = 0x52010,
5086 .halt_reg = 0x1e3a4,
5089 .enable_reg = 0x52010,
5104 .halt_reg = 0x1e4d4,
5107 .enable_reg = 0x52010,
5122 .halt_reg = 0x1e604,
5125 .enable_reg = 0x52010,
5140 .halt_reg = 0x1e734,
5143 .enable_reg = 0x52010,
5158 .halt_reg = 0x1e864,
5161 .enable_reg = 0x52018,
5176 .halt_reg = 0x1e994,
5179 .enable_reg = 0x52018,
5194 .halt_reg = 0x17004,
5196 .hwcg_reg = 0x17004,
5199 .enable_reg = 0x52008,
5209 .halt_reg = 0x17008,
5211 .hwcg_reg = 0x17008,
5214 .enable_reg = 0x52008,
5224 .halt_reg = 0x18004,
5226 .hwcg_reg = 0x18004,
5229 .enable_reg = 0x52008,
5239 .halt_reg = 0x18008,
5241 .hwcg_reg = 0x18008,
5244 .enable_reg = 0x52008,
5254 .halt_reg = 0x1e004,
5256 .hwcg_reg = 0x1e004,
5259 .enable_reg = 0x52010,
5269 .halt_reg = 0x1e008,
5271 .hwcg_reg = 0x1e008,
5274 .enable_reg = 0x52010,
5284 .halt_reg = 0x14008,
5287 .enable_reg = 0x14008,
5288 .enable_mask = BIT(0),
5297 .halt_reg = 0x14004,
5300 .enable_reg = 0x14004,
5301 .enable_mask = BIT(0),
5315 .halt_reg = 0x16008,
5318 .enable_reg = 0x16008,
5319 .enable_mask = BIT(0),
5328 .halt_reg = 0x16004,
5331 .enable_reg = 0x16004,
5332 .enable_mask = BIT(0),
5346 .halt_reg = 0x5d000,
5348 .hwcg_reg = 0x5d000,
5351 .enable_reg = 0x5d000,
5352 .enable_mask = BIT(0),
5361 .halt_reg = 0x8c000,
5364 .enable_reg = 0x8c000,
5365 .enable_mask = BIT(0),
5376 .halt_reg = 0x75018,
5378 .hwcg_reg = 0x75018,
5381 .enable_reg = 0x75018,
5382 .enable_mask = BIT(0),
5391 .halt_reg = 0x75010,
5393 .hwcg_reg = 0x75010,
5396 .enable_reg = 0x75010,
5397 .enable_mask = BIT(0),
5411 .halt_reg = 0x75010,
5413 .hwcg_reg = 0x75010,
5416 .enable_reg = 0x75010,
5431 .halt_reg = 0x8c054,
5434 .enable_reg = 0x8c054,
5435 .enable_mask = BIT(0),
5446 .halt_reg = 0x75064,
5448 .hwcg_reg = 0x75064,
5451 .enable_reg = 0x75064,
5452 .enable_mask = BIT(0),
5466 .halt_reg = 0x75064,
5468 .hwcg_reg = 0x75064,
5471 .enable_reg = 0x75064,
5486 .halt_reg = 0x7509c,
5488 .hwcg_reg = 0x7509c,
5491 .enable_reg = 0x7509c,
5492 .enable_mask = BIT(0),
5506 .halt_reg = 0x7509c,
5508 .hwcg_reg = 0x7509c,
5511 .enable_reg = 0x7509c,
5526 .halt_reg = 0x75020,
5529 .enable_reg = 0x75020,
5530 .enable_mask = BIT(0),
5544 .halt_reg = 0x750b8,
5547 .enable_reg = 0x750b8,
5548 .enable_mask = BIT(0),
5562 .halt_reg = 0x7501c,
5565 .enable_reg = 0x7501c,
5566 .enable_mask = BIT(0),
5580 .halt_reg = 0x7505c,
5582 .hwcg_reg = 0x7505c,
5585 .enable_reg = 0x7505c,
5586 .enable_mask = BIT(0),
5600 .halt_reg = 0x7505c,
5602 .hwcg_reg = 0x7505c,
5605 .enable_reg = 0x7505c,
5620 .halt_reg = 0x77018,
5622 .hwcg_reg = 0x77018,
5625 .enable_reg = 0x77018,
5626 .enable_mask = BIT(0),
5635 .halt_reg = 0x77010,
5637 .hwcg_reg = 0x77010,
5640 .enable_reg = 0x77010,
5641 .enable_mask = BIT(0),
5655 .halt_reg = 0x77010,
5657 .hwcg_reg = 0x77010,
5660 .enable_reg = 0x77010,
5675 .halt_reg = 0x77064,
5677 .hwcg_reg = 0x77064,
5680 .enable_reg = 0x77064,
5681 .enable_mask = BIT(0),
5695 .halt_reg = 0x77064,
5697 .hwcg_reg = 0x77064,
5700 .enable_reg = 0x77064,
5715 .halt_reg = 0x7709c,
5717 .hwcg_reg = 0x7709c,
5720 .enable_reg = 0x7709c,
5721 .enable_mask = BIT(0),
5735 .halt_reg = 0x7709c,
5737 .hwcg_reg = 0x7709c,
5740 .enable_reg = 0x7709c,
5755 .halt_reg = 0x77020,
5758 .enable_reg = 0x77020,
5759 .enable_mask = BIT(0),
5773 .halt_reg = 0x770b8,
5776 .enable_reg = 0x770b8,
5777 .enable_mask = BIT(0),
5791 .halt_reg = 0x7701c,
5794 .enable_reg = 0x7701c,
5795 .enable_mask = BIT(0),
5809 .halt_reg = 0x7705c,
5811 .hwcg_reg = 0x7705c,
5814 .enable_reg = 0x7705c,
5815 .enable_mask = BIT(0),
5829 .halt_reg = 0x7705c,
5831 .hwcg_reg = 0x7705c,
5834 .enable_reg = 0x7705c,
5849 .halt_reg = 0x8c058,
5852 .enable_reg = 0x8c058,
5853 .enable_mask = BIT(0),
5864 .halt_reg = 0x8c044,
5867 .enable_reg = 0x8c044,
5868 .enable_mask = BIT(0),
5877 .halt_reg = 0x8c048,
5880 .enable_reg = 0x8c048,
5881 .enable_mask = BIT(0),
5890 .halt_reg = 0x8c04c,
5893 .enable_reg = 0x8c04c,
5894 .enable_mask = BIT(0),
5903 .halt_reg = 0x8c050,
5906 .enable_reg = 0x8c050,
5907 .enable_mask = BIT(0),
5916 .halt_reg = 0xab010,
5919 .enable_reg = 0xab010,
5920 .enable_mask = BIT(0),
5934 .halt_reg = 0xab01c,
5937 .enable_reg = 0xab01c,
5938 .enable_mask = BIT(0),
5952 .halt_reg = 0xab018,
5955 .enable_reg = 0xab018,
5956 .enable_mask = BIT(0),
5965 .halt_reg = 0xf010,
5968 .enable_reg = 0xf010,
5969 .enable_mask = BIT(0),
5983 .halt_reg = 0xf01c,
5986 .enable_reg = 0xf01c,
5987 .enable_mask = BIT(0),
6001 .halt_reg = 0xf018,
6004 .enable_reg = 0xf018,
6005 .enable_mask = BIT(0),
6014 .halt_reg = 0x10010,
6017 .enable_reg = 0x10010,
6018 .enable_mask = BIT(0),
6032 .halt_reg = 0x1001c,
6035 .enable_reg = 0x1001c,
6036 .enable_mask = BIT(0),
6050 .halt_reg = 0x10018,
6053 .enable_reg = 0x10018,
6054 .enable_mask = BIT(0),
6063 .halt_reg = 0x8c03c,
6066 .enable_reg = 0x8c03c,
6067 .enable_mask = BIT(0),
6076 .halt_reg = 0x8c040,
6079 .enable_reg = 0x8c040,
6080 .enable_mask = BIT(0),
6089 .halt_reg = 0xab054,
6092 .enable_reg = 0xab054,
6093 .enable_mask = BIT(0),
6107 .halt_reg = 0xab058,
6110 .enable_reg = 0xab058,
6111 .enable_mask = BIT(0),
6125 .halt_reg = 0xab05c,
6128 .enable_reg = 0xab05c,
6129 .enable_mask = BIT(0),
6143 .halt_reg = 0xab064,
6146 .enable_reg = 0xab064,
6147 .enable_mask = BIT(0),
6161 .halt_reg = 0xf054,
6164 .enable_reg = 0xf054,
6165 .enable_mask = BIT(0),
6179 .halt_reg = 0xf058,
6182 .enable_reg = 0xf058,
6183 .enable_mask = BIT(0),
6197 .halt_reg = 0xf05c,
6199 .hwcg_reg = 0xf05c,
6202 .enable_reg = 0xf05c,
6203 .enable_mask = BIT(0),
6217 .halt_reg = 0x10054,
6220 .enable_reg = 0x10054,
6221 .enable_mask = BIT(0),
6235 .halt_reg = 0x10058,
6238 .enable_reg = 0x10058,
6239 .enable_mask = BIT(0),
6253 .halt_reg = 0x1005c,
6255 .hwcg_reg = 0x1005c,
6258 .enable_reg = 0x1005c,
6259 .enable_mask = BIT(0),
6273 .halt_reg = 0xb808c,
6275 .hwcg_reg = 0xb808c,
6278 .enable_reg = 0xb808c,
6279 .enable_mask = BIT(0),
6288 .halt_reg = 0xb8048,
6291 .enable_reg = 0xb8048,
6292 .enable_mask = BIT(0),
6306 .halt_reg = 0xb8010,
6309 .enable_reg = 0xb8010,
6310 .enable_mask = BIT(0),
6324 .halt_reg = 0xb80b4,
6327 .enable_reg = 0xb80b4,
6328 .enable_mask = BIT(0),
6342 .halt_reg = 0xb8038,
6345 .enable_reg = 0x52020,
6360 .halt_reg = 0xb8094,
6363 .enable_reg = 0xb8094,
6364 .enable_mask = BIT(0),
6378 .halt_reg = 0xb80a0,
6381 .enable_reg = 0xb80a0,
6382 .enable_mask = BIT(0),
6396 .halt_reg = 0xb8088,
6398 .hwcg_reg = 0xb8088,
6401 .enable_reg = 0xb8088,
6402 .enable_mask = BIT(0),
6416 .halt_reg = 0xb8034,
6419 .enable_reg = 0xb8034,
6420 .enable_mask = BIT(0),
6434 .halt_reg = 0xb8040,
6437 .enable_reg = 0xb8040,
6438 .enable_mask = BIT(0),
6452 .halt_reg = 0xb806c,
6454 .hwcg_reg = 0xb806c,
6457 .enable_reg = 0xb806c,
6458 .enable_mask = BIT(0),
6472 .halt_reg = 0x2a08c,
6474 .hwcg_reg = 0x2a08c,
6477 .enable_reg = 0x2a08c,
6478 .enable_mask = BIT(0),
6487 .halt_reg = 0x8c010,
6490 .enable_reg = 0x8c010,
6491 .enable_mask = BIT(0),
6500 .halt_reg = 0x2a048,
6503 .enable_reg = 0x2a048,
6504 .enable_mask = BIT(0),
6518 .halt_reg = 0x8c02c,
6521 .enable_reg = 0x8c02c,
6522 .enable_mask = BIT(0),
6531 .halt_reg = 0x2a010,
6534 .enable_reg = 0x2a010,
6535 .enable_mask = BIT(0),
6549 .halt_reg = 0x2a0b4,
6552 .enable_reg = 0x2a0b4,
6553 .enable_mask = BIT(0),
6567 .halt_reg = 0x2a038,
6570 .enable_reg = 0x52020,
6585 .halt_reg = 0x2a094,
6588 .enable_reg = 0x2a094,
6589 .enable_mask = BIT(0),
6603 .halt_reg = 0x2a0a0,
6606 .enable_reg = 0x2a0a0,
6607 .enable_mask = BIT(0),
6621 .halt_reg = 0x2a088,
6623 .hwcg_reg = 0x2a088,
6626 .enable_reg = 0x2a088,
6627 .enable_mask = BIT(0),
6641 .halt_reg = 0x2a034,
6644 .enable_reg = 0x2a034,
6645 .enable_mask = BIT(0),
6659 .halt_reg = 0x2a040,
6662 .enable_reg = 0x2a040,
6663 .enable_mask = BIT(0),
6677 .halt_reg = 0x2a06c,
6679 .hwcg_reg = 0x2a06c,
6682 .enable_reg = 0x2a06c,
6683 .enable_mask = BIT(0),
6697 .halt_reg = 0x28010,
6699 .hwcg_reg = 0x28010,
6702 .enable_reg = 0x28010,
6703 .enable_mask = BIT(0),
6712 .halt_reg = 0x28018,
6714 .hwcg_reg = 0x28018,
6717 .enable_reg = 0x28018,
6718 .enable_mask = BIT(0),
6727 .halt_reg = 0x28024,
6729 .hwcg_reg = 0x28024,
6732 .enable_reg = 0x28024,
6733 .enable_mask = BIT(0),
6742 .halt_reg = 0x28020,
6744 .hwcg_reg = 0x28020,
6747 .enable_reg = 0x28020,
6748 .enable_mask = BIT(0),
6757 .gdscr = 0xa4004,
6758 .collapse_ctrl = 0x52128,
6759 .collapse_mask = BIT(0),
6768 .gdscr = 0x8d004,
6769 .collapse_ctrl = 0x52128,
6783 .gdscr = 0x9d004,
6784 .collapse_ctrl = 0x52128,
6794 .gdscr = 0x9e004,
6795 .collapse_ctrl = 0x52128,
6805 .gdscr = 0xa0004,
6806 .collapse_ctrl = 0x52128,
6816 .gdscr = 0xa2004,
6817 .collapse_ctrl = 0x52128,
6827 .gdscr = 0x6b004,
6828 .collapse_ctrl = 0x52128,
6838 .gdscr = 0x75004,
6847 .gdscr = 0x77004,
6856 .gdscr = 0xab004,
6865 .gdscr = 0xf004,
6874 .gdscr = 0x10004,
6883 .gdscr = 0xaa004,
6892 .gdscr = 0xba004,
6901 .gdscr = 0xb8004,
6910 .gdscr = 0x2a004,
6919 .gdscr = 0x7d050,
6928 .gdscr = 0x7d058,
6937 .gdscr = 0x7d054,
6946 .gdscr = 0x7d06c,
6955 .gdscr = 0x7d05c,
6964 .gdscr = 0x7d060,
6973 .gdscr = 0x7d0a0,
6982 .gdscr = 0x7d0a4,
7374 [GCC_EMAC0_BCR] = { 0xaa000 },
7375 [GCC_EMAC1_BCR] = { 0xba000 },
7376 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
7377 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
7378 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
7379 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
7380 [GCC_PCIE_0_TUNNEL_BCR] = { 0xa4000 },
7381 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
7382 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
7383 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
7384 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
7385 [GCC_PCIE_1_TUNNEL_BCR] = { 0x8d000 },
7386 [GCC_PCIE_2A_BCR] = { 0x9d000 },
7387 [GCC_PCIE_2A_LINK_DOWN_BCR] = { 0x9d13c },
7388 [GCC_PCIE_2A_NOCSR_COM_PHY_BCR] = { 0x9d148 },
7389 [GCC_PCIE_2A_PHY_BCR] = { 0x9d144 },
7390 [GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR] = { 0x9d14c },
7391 [GCC_PCIE_2B_BCR] = { 0x9e000 },
7392 [GCC_PCIE_2B_LINK_DOWN_BCR] = { 0x9e084 },
7393 [GCC_PCIE_2B_NOCSR_COM_PHY_BCR] = { 0x9e090 },
7394 [GCC_PCIE_2B_PHY_BCR] = { 0x9e08c },
7395 [GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR] = { 0x9e094 },
7396 [GCC_PCIE_3A_BCR] = { 0xa0000 },
7397 [GCC_PCIE_3A_LINK_DOWN_BCR] = { 0xa00f0 },
7398 [GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0xa00fc },
7399 [GCC_PCIE_3A_PHY_BCR] = { 0xa00e0 },
7400 [GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0xa00e4 },
7401 [GCC_PCIE_3B_BCR] = { 0xa2000 },
7402 [GCC_PCIE_3B_LINK_DOWN_BCR] = { 0xa20e0 },
7403 [GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0xa20ec },
7404 [GCC_PCIE_3B_PHY_BCR] = { 0xa20e8 },
7405 [GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0xa20f0 },
7406 [GCC_PCIE_4_BCR] = { 0x6b000 },
7407 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0x6b300 },
7408 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x6b30c },
7409 [GCC_PCIE_4_PHY_BCR] = { 0x6b308 },
7410 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x6b310 },
7411 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
7412 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
7413 [GCC_PCIE_RSCC_BCR] = { 0xae000 },
7414 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x12008 },
7415 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x1200c },
7416 [GCC_QUSB2PHY_HS2_MP_BCR] = { 0x12010 },
7417 [GCC_QUSB2PHY_HS3_MP_BCR] = { 0x12014 },
7418 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
7419 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
7420 [GCC_SDCC2_BCR] = { 0x14000 },
7421 [GCC_SDCC4_BCR] = { 0x16000 },
7422 [GCC_UFS_CARD_BCR] = { 0x75000 },
7423 [GCC_UFS_PHY_BCR] = { 0x77000 },
7424 [GCC_USB2_PHY_PRIM_BCR] = { 0x50028 },
7425 [GCC_USB2_PHY_SEC_BCR] = { 0x5002c },
7426 [GCC_USB30_MP_BCR] = { 0xab000 },
7427 [GCC_USB30_PRIM_BCR] = { 0xf000 },
7428 [GCC_USB30_SEC_BCR] = { 0x10000 },
7429 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
7430 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
7431 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
7432 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
7433 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x50018 },
7434 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5001c },
7435 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
7436 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
7437 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x50020 },
7438 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50024 },
7439 [GCC_USB4_1_BCR] = { 0xb8000 },
7440 [GCC_USB4_1_DP_PHY_PRIM_BCR] = { 0xb9020 },
7441 [GCC_USB4_1_DPPHY_AUX_BCR] = { 0xb9024 },
7442 [GCC_USB4_1_PHY_PRIM_BCR] = { 0xb9018 },
7443 [GCC_USB4_BCR] = { 0x2a000 },
7444 [GCC_USB4_DP_PHY_PRIM_BCR] = { 0x4a008 },
7445 [GCC_USB4_DPPHY_AUX_BCR] = { 0x4a00c },
7446 [GCC_USB4_PHY_PRIM_BCR] = { 0x4a000 },
7447 [GCC_USB4PHY_1_PHY_PRIM_BCR] = { 0xb901c },
7448 [GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 },
7449 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
7450 [GCC_VIDEO_BCR] = { 0x28000 },
7451 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
7452 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
7513 .max_register = 0xc3014,
7547 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ in gcc_sc8280xp_probe()
7548 qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */ in gcc_sc8280xp_probe()
7549 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ in gcc_sc8280xp_probe()
7550 qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */ in gcc_sc8280xp_probe()
7551 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sc8280xp_probe()
7552 qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ in gcc_sc8280xp_probe()
7553 qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */ in gcc_sc8280xp_probe()
7554 qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */ in gcc_sc8280xp_probe()
7555 qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */ in gcc_sc8280xp_probe()
7567 return 0; in gcc_sc8280xp_probe()