Lines Matching +full:0 +full:x12010
43 { 249600000, 2000000000, 0 },
47 .offset = 0x0,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
66 { 0x0, 1 },
67 { 0x1, 2 },
68 { 0x3, 4 },
69 { 0x7, 8 },
74 .offset = 0x0,
89 .offset = 0x1000,
94 .enable_reg = 0x52000,
108 .offset = 0x76000,
113 .enable_reg = 0x52000,
127 .offset = 0x1a000,
132 .enable_reg = 0x52000,
146 .offset = 0x1c000,
149 .enable_reg = 0x52000,
163 { P_BI_TCXO, 0 },
175 { P_BI_TCXO, 0 },
189 { P_BI_TCXO, 0 },
199 { P_BI_TCXO, 0 },
219 { P_BI_TCXO, 0 },
227 { P_BI_TCXO, 0 },
237 { P_BI_TCXO, 0 },
251 { P_BI_TCXO, 0 },
267 { P_BI_TCXO, 0 },
281 F(19200000, P_BI_TCXO, 1, 0, 0),
282 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
283 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
284 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
289 .cmd_rcgr = 0x6038,
290 .mnd_width = 0,
306 F(19200000, P_BI_TCXO, 1, 0, 0),
307 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
308 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
309 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
310 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
315 .cmd_rcgr = 0x601c,
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
332 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
333 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
334 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
339 .cmd_rcgr = 0x64004,
354 .cmd_rcgr = 0x65004,
369 .cmd_rcgr = 0x66004,
384 .cmd_rcgr = 0xbe004,
399 .cmd_rcgr = 0xbf004,
414 F(19200000, P_BI_TCXO, 1, 0, 0),
415 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
416 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
417 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
418 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
419 F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
420 F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
425 .cmd_rcgr = 0x4d014,
426 .mnd_width = 0,
440 F(9600000, P_BI_TCXO, 2, 0, 0),
441 F(19200000, P_BI_TCXO, 1, 0, 0),
446 .cmd_rcgr = 0x6b02c,
461 .cmd_rcgr = 0x8d02c,
476 .cmd_rcgr = 0x9d02c,
491 .cmd_rcgr = 0xa302c,
506 F(19200000, P_BI_TCXO, 1, 0, 0),
507 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
512 .cmd_rcgr = 0x6f014,
513 .mnd_width = 0,
527 F(9600000, P_BI_TCXO, 2, 0, 0),
528 F(19200000, P_BI_TCXO, 1, 0, 0),
529 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
534 .cmd_rcgr = 0x33010,
535 .mnd_width = 0,
549 F(19200000, P_BI_TCXO, 1, 0, 0),
550 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
551 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
552 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
557 .cmd_rcgr = 0x4a00c,
558 .mnd_width = 0,
572 .cmd_rcgr = 0x4b008,
573 .mnd_width = 0,
589 F(19200000, P_BI_TCXO, 1, 0, 0),
593 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
595 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
598 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
602 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
616 .cmd_rcgr = 0x17148,
633 .cmd_rcgr = 0x17278,
650 .cmd_rcgr = 0x173a8,
667 .cmd_rcgr = 0x174d8,
684 .cmd_rcgr = 0x17608,
701 .cmd_rcgr = 0x17738,
718 .cmd_rcgr = 0x17868,
735 .cmd_rcgr = 0x17998,
752 .cmd_rcgr = 0x18148,
769 .cmd_rcgr = 0x18278,
786 .cmd_rcgr = 0x183a8,
803 .cmd_rcgr = 0x184d8,
820 .cmd_rcgr = 0x18608,
837 .cmd_rcgr = 0x18738,
854 .cmd_rcgr = 0x1e148,
871 .cmd_rcgr = 0x1e278,
889 .cmd_rcgr = 0x1e3a8,
906 .cmd_rcgr = 0x1e4d8,
923 .cmd_rcgr = 0x1e608,
940 .cmd_rcgr = 0x1e738,
950 F(9600000, P_BI_TCXO, 2, 0, 0),
951 F(19200000, P_BI_TCXO, 1, 0, 0),
953 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
954 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
955 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
960 .cmd_rcgr = 0x1400c,
976 F(9600000, P_BI_TCXO, 2, 0, 0),
977 F(19200000, P_BI_TCXO, 1, 0, 0),
978 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
979 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
984 .cmd_rcgr = 0x1600c,
1004 .cmd_rcgr = 0x36010,
1019 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1020 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1021 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1022 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1027 .cmd_rcgr = 0xa2020,
1042 .cmd_rcgr = 0xa2060,
1043 .mnd_width = 0,
1057 F(19200000, P_BI_TCXO, 1, 0, 0),
1062 .cmd_rcgr = 0xa2094,
1063 .mnd_width = 0,
1077 .cmd_rcgr = 0xa2078,
1078 .mnd_width = 0,
1092 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1093 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1094 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1095 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1096 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1101 .cmd_rcgr = 0x75020,
1116 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1117 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1118 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1123 .cmd_rcgr = 0x75060,
1124 .mnd_width = 0,
1138 .cmd_rcgr = 0x75094,
1139 .mnd_width = 0,
1153 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1154 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1155 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1160 .cmd_rcgr = 0x75078,
1161 .mnd_width = 0,
1175 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1176 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1177 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1178 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1179 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1184 .cmd_rcgr = 0x77020,
1199 .cmd_rcgr = 0x77060,
1200 .mnd_width = 0,
1214 .cmd_rcgr = 0x77094,
1215 .mnd_width = 0,
1229 .cmd_rcgr = 0x77078,
1230 .mnd_width = 0,
1244 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1245 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1246 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1247 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1248 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1253 .cmd_rcgr = 0xa601c,
1268 F(19200000, P_BI_TCXO, 1, 0, 0),
1269 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1270 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1271 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1276 .cmd_rcgr = 0xa6034,
1277 .mnd_width = 0,
1291 .cmd_rcgr = 0xf01c,
1306 .cmd_rcgr = 0xf034,
1307 .mnd_width = 0,
1321 .cmd_rcgr = 0x1001c,
1336 .cmd_rcgr = 0x10034,
1337 .mnd_width = 0,
1351 .cmd_rcgr = 0xa6068,
1352 .mnd_width = 0,
1366 .cmd_rcgr = 0xf060,
1367 .mnd_width = 0,
1381 .cmd_rcgr = 0x10060,
1382 .mnd_width = 0,
1396 .halt_reg = 0x90018,
1399 .enable_reg = 0x90018,
1400 .enable_mask = BIT(0),
1409 .halt_reg = 0x750c0,
1411 .hwcg_reg = 0x750c0,
1414 .enable_reg = 0x750c0,
1415 .enable_mask = BIT(0),
1429 .halt_reg = 0x750c0,
1431 .hwcg_reg = 0x750c0,
1434 .enable_reg = 0x750c0,
1449 .halt_reg = 0x770c0,
1451 .hwcg_reg = 0x770c0,
1454 .enable_reg = 0x770c0,
1455 .enable_mask = BIT(0),
1469 .halt_reg = 0x770c0,
1471 .hwcg_reg = 0x770c0,
1474 .enable_reg = 0x770c0,
1489 .halt_reg = 0xa6084,
1492 .enable_reg = 0xa6084,
1493 .enable_mask = BIT(0),
1507 .halt_reg = 0xf07c,
1510 .enable_reg = 0xf07c,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0x1007c,
1528 .enable_reg = 0x1007c,
1529 .enable_mask = BIT(0),
1543 .halt_reg = 0x38004,
1545 .hwcg_reg = 0x38004,
1548 .enable_reg = 0x52004,
1558 .halt_reg = 0xb030,
1561 .enable_reg = 0xb030,
1562 .enable_mask = BIT(0),
1571 .halt_reg = 0xb034,
1574 .enable_reg = 0xb034,
1575 .enable_mask = BIT(0),
1584 .halt_reg = 0xa609c,
1587 .enable_reg = 0xa609c,
1588 .enable_mask = BIT(0),
1602 .halt_reg = 0xf078,
1605 .enable_reg = 0xf078,
1606 .enable_mask = BIT(0),
1620 .halt_reg = 0x10078,
1623 .enable_reg = 0x10078,
1624 .enable_mask = BIT(0),
1638 .halt_reg = 0x48008,
1641 .enable_reg = 0x48008,
1642 .enable_mask = BIT(0),
1651 .halt_reg = 0x71154,
1654 .enable_reg = 0x71154,
1655 .enable_mask = BIT(0),
1664 .halt_reg = 0xb038,
1667 .enable_reg = 0xb038,
1668 .enable_mask = BIT(0),
1677 .halt_reg = 0xb03c,
1680 .enable_reg = 0xb03c,
1681 .enable_mask = BIT(0),
1690 .halt_reg = 0x6010,
1693 .enable_reg = 0x6010,
1694 .enable_mask = BIT(0),
1703 .halt_reg = 0x6034,
1706 .enable_reg = 0x6034,
1707 .enable_mask = BIT(0),
1721 .halt_reg = 0x6018,
1724 .enable_reg = 0x6018,
1725 .enable_mask = BIT(0),
1739 .halt_reg = 0x6014,
1741 .hwcg_reg = 0x6014,
1744 .enable_reg = 0x6014,
1745 .enable_mask = BIT(0),
1754 .halt_reg = 0x64000,
1757 .enable_reg = 0x64000,
1758 .enable_mask = BIT(0),
1772 .halt_reg = 0x65000,
1775 .enable_reg = 0x65000,
1776 .enable_mask = BIT(0),
1790 .halt_reg = 0x66000,
1793 .enable_reg = 0x66000,
1794 .enable_mask = BIT(0),
1808 .halt_reg = 0xbe000,
1811 .enable_reg = 0xbe000,
1812 .enable_mask = BIT(0),
1826 .halt_reg = 0xbf000,
1829 .enable_reg = 0xbf000,
1830 .enable_mask = BIT(0),
1846 .enable_reg = 0x52004,
1861 .enable_reg = 0x52004,
1876 .halt_reg = 0x7100c,
1879 .enable_reg = 0x7100c,
1880 .enable_mask = BIT(0),
1889 .halt_reg = 0x71018,
1892 .enable_reg = 0x71018,
1893 .enable_mask = BIT(0),
1902 .halt_reg = 0x4d010,
1905 .enable_reg = 0x4d010,
1906 .enable_mask = BIT(0),
1915 .halt_reg = 0x4d008,
1918 .enable_reg = 0x4d008,
1919 .enable_mask = BIT(0),
1935 .enable_reg = 0x52004,
1950 .enable_reg = 0x52004,
1965 .halt_reg = 0x4d00c,
1968 .enable_reg = 0x4d00c,
1969 .enable_mask = BIT(0),
1978 .halt_reg = 0x6f02c,
1981 .enable_reg = 0x6f02c,
1982 .enable_mask = BIT(0),
1996 .halt_reg = 0x6f030,
1999 .enable_reg = 0x6f030,
2000 .enable_mask = BIT(0),
2014 .halt_reg = 0x6f034,
2017 .enable_reg = 0x6f034,
2018 .enable_mask = BIT(0),
2032 .halt_reg = 0x6f038,
2035 .enable_reg = 0x6f038,
2036 .enable_mask = BIT(0),
2050 .halt_reg = 0x6b020,
2053 .enable_reg = 0x5200c,
2068 .halt_reg = 0x6b01c,
2070 .hwcg_reg = 0x6b01c,
2073 .enable_reg = 0x5200c,
2083 .halt_reg = 0x8c00c,
2086 .enable_reg = 0x8c00c,
2087 .enable_mask = BIT(0),
2096 .halt_reg = 0x6b018,
2099 .enable_reg = 0x5200c,
2109 .halt_reg = 0x6b024,
2112 .enable_reg = 0x5200c,
2122 .halt_reg = 0x6b014,
2124 .hwcg_reg = 0x6b014,
2127 .enable_reg = 0x5200c,
2128 .enable_mask = BIT(0),
2137 .halt_reg = 0x6b010,
2140 .enable_reg = 0x5200c,
2150 .halt_reg = 0x8d020,
2153 .enable_reg = 0x52004,
2168 .halt_reg = 0x8d01c,
2170 .hwcg_reg = 0x8d01c,
2173 .enable_reg = 0x52004,
2183 .halt_reg = 0x8c02c,
2186 .enable_reg = 0x8c02c,
2187 .enable_mask = BIT(0),
2196 .halt_reg = 0x8d018,
2199 .enable_reg = 0x52004,
2209 .halt_reg = 0x8d024,
2212 .enable_reg = 0x52004,
2222 .halt_reg = 0x8d014,
2224 .hwcg_reg = 0x8d014,
2227 .enable_reg = 0x52004,
2237 .halt_reg = 0x8d010,
2240 .enable_reg = 0x52004,
2250 .halt_reg = 0x9d020,
2253 .enable_reg = 0x52014,
2268 .halt_reg = 0x9d01c,
2270 .hwcg_reg = 0x9d01c,
2273 .enable_reg = 0x52014,
2283 .halt_reg = 0x8c014,
2286 .enable_reg = 0x8c014,
2287 .enable_mask = BIT(0),
2296 .halt_reg = 0x9d018,
2299 .enable_reg = 0x52014,
2309 .halt_reg = 0x9d024,
2312 .enable_reg = 0x52014,
2322 .halt_reg = 0x9d014,
2324 .hwcg_reg = 0x9d014,
2327 .enable_reg = 0x52014,
2337 .halt_reg = 0x9d010,
2340 .enable_reg = 0x52014,
2350 .halt_reg = 0xa3020,
2353 .enable_reg = 0x52014,
2368 .halt_reg = 0xa301c,
2370 .hwcg_reg = 0xa301c,
2373 .enable_reg = 0x52014,
2383 .halt_reg = 0x8c018,
2386 .enable_reg = 0x8c018,
2387 .enable_mask = BIT(0),
2396 .halt_reg = 0xa3018,
2399 .enable_reg = 0x52014,
2409 .halt_reg = 0xa3024,
2412 .enable_reg = 0x52014,
2422 .halt_reg = 0xa3014,
2424 .hwcg_reg = 0xa3014,
2427 .enable_reg = 0x52014,
2437 .halt_reg = 0xa3010,
2440 .enable_reg = 0x52014,
2450 .halt_reg = 0x6f004,
2453 .enable_reg = 0x6f004,
2454 .enable_mask = BIT(0),
2468 .halt_reg = 0x3300c,
2471 .enable_reg = 0x3300c,
2472 .enable_mask = BIT(0),
2486 .halt_reg = 0x33004,
2488 .hwcg_reg = 0x33004,
2491 .enable_reg = 0x33004,
2492 .enable_mask = BIT(0),
2501 .halt_reg = 0x33008,
2504 .enable_reg = 0x33008,
2505 .enable_mask = BIT(0),
2514 .halt_reg = 0x34004,
2517 .enable_reg = 0x52004,
2527 .halt_reg = 0xb018,
2529 .hwcg_reg = 0xb018,
2532 .enable_reg = 0xb018,
2533 .enable_mask = BIT(0),
2542 .halt_reg = 0xb01c,
2544 .hwcg_reg = 0xb01c,
2547 .enable_reg = 0xb01c,
2548 .enable_mask = BIT(0),
2557 .halt_reg = 0xb020,
2559 .hwcg_reg = 0xb020,
2562 .enable_reg = 0xb020,
2563 .enable_mask = BIT(0),
2572 .halt_reg = 0xb010,
2574 .hwcg_reg = 0xb010,
2577 .enable_reg = 0xb010,
2578 .enable_mask = BIT(0),
2587 .halt_reg = 0xb014,
2589 .hwcg_reg = 0xb014,
2592 .enable_reg = 0xb014,
2593 .enable_mask = BIT(0),
2602 .halt_reg = 0x4a004,
2605 .enable_reg = 0x4a004,
2606 .enable_mask = BIT(0),
2615 .halt_reg = 0x4a008,
2618 .enable_reg = 0x4a008,
2619 .enable_mask = BIT(0),
2633 .halt_reg = 0x4b000,
2636 .enable_reg = 0x4b000,
2637 .enable_mask = BIT(0),
2646 .halt_reg = 0x4b004,
2649 .enable_reg = 0x4b004,
2650 .enable_mask = BIT(0),
2664 .halt_reg = 0x17144,
2667 .enable_reg = 0x5200c,
2682 .halt_reg = 0x17274,
2685 .enable_reg = 0x5200c,
2700 .halt_reg = 0x173a4,
2703 .enable_reg = 0x5200c,
2718 .halt_reg = 0x174d4,
2721 .enable_reg = 0x5200c,
2736 .halt_reg = 0x17604,
2739 .enable_reg = 0x5200c,
2754 .halt_reg = 0x17734,
2757 .enable_reg = 0x5200c,
2772 .halt_reg = 0x17864,
2775 .enable_reg = 0x5200c,
2790 .halt_reg = 0x17994,
2793 .enable_reg = 0x5200c,
2808 .halt_reg = 0x18144,
2811 .enable_reg = 0x5200c,
2826 .halt_reg = 0x18274,
2829 .enable_reg = 0x5200c,
2844 .halt_reg = 0x183a4,
2847 .enable_reg = 0x5200c,
2862 .halt_reg = 0x184d4,
2865 .enable_reg = 0x5200c,
2880 .halt_reg = 0x18604,
2883 .enable_reg = 0x5200c,
2898 .halt_reg = 0x18734,
2901 .enable_reg = 0x5200c,
2916 .halt_reg = 0x1e144,
2919 .enable_reg = 0x52014,
2934 .halt_reg = 0x1e274,
2937 .enable_reg = 0x52014,
2952 .halt_reg = 0x1e3a4,
2955 .enable_reg = 0x52014,
2970 .halt_reg = 0x1e4d4,
2973 .enable_reg = 0x52014,
2988 .halt_reg = 0x1e604,
2991 .enable_reg = 0x52014,
3006 .halt_reg = 0x1e734,
3009 .enable_reg = 0x52014,
3024 .halt_reg = 0x17004,
3027 .enable_reg = 0x5200c,
3037 .halt_reg = 0x17008,
3039 .hwcg_reg = 0x17008,
3042 .enable_reg = 0x5200c,
3052 .halt_reg = 0x18004,
3055 .enable_reg = 0x5200c,
3065 .halt_reg = 0x18008,
3067 .hwcg_reg = 0x18008,
3070 .enable_reg = 0x5200c,
3080 .halt_reg = 0x1e004,
3083 .enable_reg = 0x52014,
3093 .halt_reg = 0x1e008,
3095 .hwcg_reg = 0x1e008,
3098 .enable_reg = 0x52014,
3108 .halt_reg = 0x14008,
3111 .enable_reg = 0x14008,
3112 .enable_mask = BIT(0),
3121 .halt_reg = 0x14004,
3124 .enable_reg = 0x14004,
3125 .enable_mask = BIT(0),
3139 .halt_reg = 0x16008,
3142 .enable_reg = 0x16008,
3143 .enable_mask = BIT(0),
3152 .halt_reg = 0x16004,
3155 .enable_reg = 0x16004,
3156 .enable_mask = BIT(0),
3170 .halt_reg = 0x36004,
3173 .enable_reg = 0x36004,
3174 .enable_mask = BIT(0),
3183 .halt_reg = 0x3600c,
3186 .enable_reg = 0x3600c,
3187 .enable_mask = BIT(0),
3196 .halt_reg = 0x36008,
3199 .enable_reg = 0x36008,
3200 .enable_mask = BIT(0),
3214 .halt_reg = 0xa2014,
3216 .hwcg_reg = 0xa2014,
3219 .enable_reg = 0xa2014,
3220 .enable_mask = BIT(0),
3229 .halt_reg = 0xa2010,
3231 .hwcg_reg = 0xa2010,
3234 .enable_reg = 0xa2010,
3235 .enable_mask = BIT(0),
3249 .halt_reg = 0xa205c,
3251 .hwcg_reg = 0xa205c,
3254 .enable_reg = 0xa205c,
3255 .enable_mask = BIT(0),
3269 .halt_reg = 0xa2090,
3271 .hwcg_reg = 0xa2090,
3274 .enable_reg = 0xa2090,
3275 .enable_mask = BIT(0),
3289 .halt_reg = 0xa201c,
3292 .enable_reg = 0xa201c,
3293 .enable_mask = BIT(0),
3302 .halt_reg = 0xa20ac,
3305 .enable_reg = 0xa20ac,
3306 .enable_mask = BIT(0),
3315 .halt_reg = 0xa2018,
3318 .enable_reg = 0xa2018,
3319 .enable_mask = BIT(0),
3328 .halt_reg = 0xa2058,
3330 .hwcg_reg = 0xa2058,
3333 .enable_reg = 0xa2058,
3334 .enable_mask = BIT(0),
3348 .halt_reg = 0x8c004,
3351 .enable_reg = 0x8c004,
3352 .enable_mask = BIT(0),
3361 .halt_reg = 0x75014,
3363 .hwcg_reg = 0x75014,
3366 .enable_reg = 0x75014,
3367 .enable_mask = BIT(0),
3376 .halt_reg = 0x75010,
3378 .hwcg_reg = 0x75010,
3381 .enable_reg = 0x75010,
3382 .enable_mask = BIT(0),
3396 .halt_reg = 0x75010,
3398 .hwcg_reg = 0x75010,
3401 .enable_reg = 0x75010,
3416 .halt_reg = 0x7505c,
3418 .hwcg_reg = 0x7505c,
3421 .enable_reg = 0x7505c,
3422 .enable_mask = BIT(0),
3436 .halt_reg = 0x7505c,
3438 .hwcg_reg = 0x7505c,
3441 .enable_reg = 0x7505c,
3456 .halt_reg = 0x75090,
3458 .hwcg_reg = 0x75090,
3461 .enable_reg = 0x75090,
3462 .enable_mask = BIT(0),
3476 .halt_reg = 0x75090,
3478 .hwcg_reg = 0x75090,
3481 .enable_reg = 0x75090,
3496 .halt_reg = 0x7501c,
3499 .enable_reg = 0x7501c,
3500 .enable_mask = BIT(0),
3509 .halt_reg = 0x750ac,
3512 .enable_reg = 0x750ac,
3513 .enable_mask = BIT(0),
3522 .halt_reg = 0x75018,
3525 .enable_reg = 0x75018,
3526 .enable_mask = BIT(0),
3535 .halt_reg = 0x75058,
3537 .hwcg_reg = 0x75058,
3540 .enable_reg = 0x75058,
3541 .enable_mask = BIT(0),
3555 .halt_reg = 0x75058,
3557 .hwcg_reg = 0x75058,
3560 .enable_reg = 0x75058,
3575 .halt_reg = 0x8c000,
3578 .enable_reg = 0x8c000,
3579 .enable_mask = BIT(0),
3588 .halt_reg = 0x77014,
3590 .hwcg_reg = 0x77014,
3593 .enable_reg = 0x77014,
3594 .enable_mask = BIT(0),
3603 .halt_reg = 0x77010,
3605 .hwcg_reg = 0x77010,
3608 .enable_reg = 0x77010,
3609 .enable_mask = BIT(0),
3623 .halt_reg = 0x77010,
3625 .hwcg_reg = 0x77010,
3628 .enable_reg = 0x77010,
3643 .halt_reg = 0x7705c,
3645 .hwcg_reg = 0x7705c,
3648 .enable_reg = 0x7705c,
3649 .enable_mask = BIT(0),
3663 .halt_reg = 0x7705c,
3665 .hwcg_reg = 0x7705c,
3668 .enable_reg = 0x7705c,
3683 .halt_reg = 0x77090,
3685 .hwcg_reg = 0x77090,
3688 .enable_reg = 0x77090,
3689 .enable_mask = BIT(0),
3703 .halt_reg = 0x77090,
3705 .hwcg_reg = 0x77090,
3708 .enable_reg = 0x77090,
3723 .halt_reg = 0x7701c,
3726 .enable_reg = 0x7701c,
3727 .enable_mask = BIT(0),
3736 .halt_reg = 0x770ac,
3739 .enable_reg = 0x770ac,
3740 .enable_mask = BIT(0),
3749 .halt_reg = 0x77018,
3752 .enable_reg = 0x77018,
3753 .enable_mask = BIT(0),
3762 .halt_reg = 0x77058,
3764 .hwcg_reg = 0x77058,
3767 .enable_reg = 0x77058,
3768 .enable_mask = BIT(0),
3782 .halt_reg = 0x77058,
3784 .hwcg_reg = 0x77058,
3787 .enable_reg = 0x77058,
3802 .halt_reg = 0xa6010,
3805 .enable_reg = 0xa6010,
3806 .enable_mask = BIT(0),
3819 .halt_reg = 0xa6018,
3822 .enable_reg = 0xa6018,
3823 .enable_mask = BIT(0),
3837 .halt_reg = 0xa6014,
3840 .enable_reg = 0xa6014,
3841 .enable_mask = BIT(0),
3850 .halt_reg = 0xf010,
3853 .enable_reg = 0xf010,
3854 .enable_mask = BIT(0),
3867 .halt_reg = 0xf018,
3870 .enable_reg = 0xf018,
3871 .enable_mask = BIT(0),
3885 .halt_reg = 0xf014,
3888 .enable_reg = 0xf014,
3889 .enable_mask = BIT(0),
3898 .halt_reg = 0x10010,
3901 .enable_reg = 0x10010,
3902 .enable_mask = BIT(0),
3915 .halt_reg = 0x10018,
3918 .enable_reg = 0x10018,
3919 .enable_mask = BIT(0),
3933 .halt_reg = 0x10014,
3936 .enable_reg = 0x10014,
3937 .enable_mask = BIT(0),
3946 .halt_reg = 0xa6050,
3949 .enable_reg = 0xa6050,
3950 .enable_mask = BIT(0),
3964 .halt_reg = 0xa6054,
3967 .enable_reg = 0xa6054,
3968 .enable_mask = BIT(0),
3982 .halt_reg = 0xa6058,
3985 .enable_reg = 0xa6058,
3986 .enable_mask = BIT(0),
3995 .halt_reg = 0xa605c,
3998 .enable_reg = 0xa605c,
3999 .enable_mask = BIT(0),
4008 .halt_reg = 0x8c008,
4011 .enable_reg = 0x8c008,
4012 .enable_mask = BIT(0),
4021 .halt_reg = 0xf050,
4024 .enable_reg = 0xf050,
4025 .enable_mask = BIT(0),
4039 .halt_reg = 0xf054,
4042 .enable_reg = 0xf054,
4043 .enable_mask = BIT(0),
4057 .halt_reg = 0xf058,
4060 .enable_reg = 0xf058,
4061 .enable_mask = BIT(0),
4070 .halt_reg = 0x8c028,
4073 .enable_reg = 0x8c028,
4074 .enable_mask = BIT(0),
4083 .halt_reg = 0x10050,
4086 .enable_reg = 0x10050,
4087 .enable_mask = BIT(0),
4101 .halt_reg = 0x10054,
4104 .enable_reg = 0x10054,
4105 .enable_mask = BIT(0),
4119 .halt_reg = 0x10058,
4122 .enable_reg = 0x10058,
4123 .enable_mask = BIT(0),
4132 .halt_reg = 0xb024,
4135 .enable_reg = 0xb024,
4136 .enable_mask = BIT(0),
4145 .halt_reg = 0xb028,
4148 .enable_reg = 0xb028,
4149 .enable_mask = BIT(0),
4158 .halt_reg = 0xb02c,
4161 .enable_reg = 0xb02c,
4162 .enable_mask = BIT(0),
4171 .gdscr = 0x10004,
4180 .gdscr = 0x6004,
4189 .gdscr = 0xf004,
4198 .gdscr = 0x6b004,
4207 .gdscr = 0x75004,
4216 .gdscr = 0x77004,
4225 .gdscr = 0x8d004,
4234 .gdscr = 0x9d004,
4243 .gdscr = 0xa2004,
4252 .gdscr = 0xa3004,
4261 .gdscr = 0xa6004,
4512 [GCC_EMAC_BCR] = { 0x6000 },
4513 [GCC_GPU_BCR] = { 0x71000 },
4514 [GCC_MMSS_BCR] = { 0xb000 },
4515 [GCC_NPU_BCR] = { 0x4d000 },
4516 [GCC_PCIE_0_BCR] = { 0x6b000 },
4517 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
4518 [GCC_PCIE_1_BCR] = { 0x8d000 },
4519 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
4520 [GCC_PCIE_2_BCR] = { 0x9d000 },
4521 [GCC_PCIE_2_PHY_BCR] = { 0xa701c },
4522 [GCC_PCIE_3_BCR] = { 0xa3000 },
4523 [GCC_PCIE_3_PHY_BCR] = { 0xa801c },
4524 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
4525 [GCC_PDM_BCR] = { 0x33000 },
4526 [GCC_PRNG_BCR] = { 0x34000 },
4527 [GCC_QSPI_1_BCR] = { 0x4a000 },
4528 [GCC_QSPI_BCR] = { 0x24008 },
4529 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
4530 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
4531 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
4532 [GCC_QUSB2PHY_5_BCR] = { 0x12010 },
4533 [GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },
4534 [GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },
4535 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
4536 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
4537 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
4538 [GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },
4539 [GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },
4540 [GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },
4541 [GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
4542 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
4543 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
4544 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x50024 },
4545 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x50028 },
4546 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5002c },
4547 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50030 },
4548 [GCC_SDCC2_BCR] = { 0x14000 },
4549 [GCC_SDCC4_BCR] = { 0x16000 },
4550 [GCC_TSIF_BCR] = { 0x36000 },
4551 [GCC_UFS_CARD_2_BCR] = { 0xa2000 },
4552 [GCC_UFS_CARD_BCR] = { 0x75000 },
4553 [GCC_UFS_PHY_BCR] = { 0x77000 },
4554 [GCC_USB30_MP_BCR] = { 0xa6000 },
4555 [GCC_USB30_PRIM_BCR] = { 0xf000 },
4556 [GCC_USB30_SEC_BCR] = { 0x10000 },
4557 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
4558 [GCC_VIDEO_AXIC_CLK_BCR] = { .reg = 0xb02c, .bit = 2, .udelay = 150 },
4559 [GCC_VIDEO_AXI0_CLK_BCR] = { .reg = 0xb024, .bit = 2, .udelay = 150 },
4560 [GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },
4604 .max_register = 0xc0004,
4634 qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ in gcc_sc8180x_probe()
4635 qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ in gcc_sc8180x_probe()
4636 qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ in gcc_sc8180x_probe()
4637 qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ in gcc_sc8180x_probe()
4638 qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ in gcc_sc8180x_probe()
4639 qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ in gcc_sc8180x_probe()
4640 qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ in gcc_sc8180x_probe()
4641 qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */ in gcc_sc8180x_probe()
4642 qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */ in gcc_sc8180x_probe()
4643 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sc8180x_probe()
4646 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sc8180x_probe()
4647 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sc8180x_probe()