Lines Matching +full:0 +full:x12010
36 .offset = 0x0,
39 .enable_reg = 0x52010,
40 .enable_mask = BIT(0),
54 { 0x1, 2 },
59 .offset = 0x0,
89 .offset = 0x01000,
92 .enable_reg = 0x52010,
107 .offset = 0x76000,
110 .enable_reg = 0x52010,
125 .offset = 0x13000,
128 .enable_reg = 0x52010,
143 .offset = 0x27000,
146 .enable_reg = 0x52010,
161 { P_BI_TCXO, 0 },
179 { P_BI_TCXO, 0 },
193 { P_BI_TCXO, 0 },
209 { P_BI_TCXO, 0 },
219 { P_BI_TCXO, 0 },
233 { P_BI_TCXO, 0 },
247 { P_BI_TCXO, 0 },
259 F(19200000, P_BI_TCXO, 1, 0, 0),
264 .cmd_rcgr = 0x48014,
265 .mnd_width = 0,
279 F(19200000, P_BI_TCXO, 1, 0, 0),
280 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
281 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
282 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
283 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
288 .cmd_rcgr = 0x64004,
302 .cmd_rcgr = 0x65004,
316 .cmd_rcgr = 0x66004,
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
336 .cmd_rcgr = 0x33010,
337 .mnd_width = 0,
350 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
351 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
352 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
357 .cmd_rcgr = 0x4b00c,
358 .mnd_width = 0,
373 F(19200000, P_BI_TCXO, 1, 0, 0),
377 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
379 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
382 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
386 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
387 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
399 .cmd_rcgr = 0x17034,
415 .cmd_rcgr = 0x17164,
431 .cmd_rcgr = 0x17294,
447 .cmd_rcgr = 0x173c4,
463 .cmd_rcgr = 0x174f4,
479 .cmd_rcgr = 0x17624,
495 .cmd_rcgr = 0x18018,
511 .cmd_rcgr = 0x18148,
527 .cmd_rcgr = 0x18278,
543 .cmd_rcgr = 0x183a8,
559 .cmd_rcgr = 0x184d8,
575 .cmd_rcgr = 0x18608,
587 F(19200000, P_BI_TCXO, 1, 0, 0),
590 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
591 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
592 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
593 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
598 .cmd_rcgr = 0x12028,
612 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
613 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
614 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
615 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
620 .cmd_rcgr = 0x12010,
621 .mnd_width = 0,
635 F(9600000, P_BI_TCXO, 2, 0, 0),
636 F(19200000, P_BI_TCXO, 1, 0, 0),
637 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
638 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
639 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
640 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
645 .cmd_rcgr = 0x1400c,
660 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
661 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
662 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
663 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
664 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
669 .cmd_rcgr = 0x77020,
683 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
684 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
685 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
686 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
691 .cmd_rcgr = 0x77048,
692 .mnd_width = 0,
705 F(9600000, P_BI_TCXO, 2, 0, 0),
706 F(19200000, P_BI_TCXO, 1, 0, 0),
711 .cmd_rcgr = 0x77098,
712 .mnd_width = 0,
725 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
726 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
727 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
732 .cmd_rcgr = 0x77060,
733 .mnd_width = 0,
746 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
747 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
748 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
749 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
754 .cmd_rcgr = 0xf01c,
768 F(19200000, P_BI_TCXO, 1, 0, 0),
769 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
774 .cmd_rcgr = 0xf034,
775 .mnd_width = 0,
788 F(19200000, P_BI_TCXO, 1, 0, 0),
793 .cmd_rcgr = 0xf060,
794 .mnd_width = 0,
807 F(4800000, P_BI_TCXO, 4, 0, 0),
808 F(19200000, P_BI_TCXO, 1, 0, 0),
813 .cmd_rcgr = 0x3d030,
814 .mnd_width = 0,
827 .halt_reg = 0x82024,
829 .hwcg_reg = 0x82024,
832 .enable_reg = 0x82024,
833 .enable_mask = BIT(0),
847 .halt_reg = 0x8201c,
850 .enable_reg = 0x8201c,
851 .enable_mask = BIT(0),
865 .halt_reg = 0x38004,
867 .hwcg_reg = 0x38004,
870 .enable_reg = 0x52000,
880 .halt_reg = 0xb020,
883 .enable_reg = 0xb020,
884 .enable_mask = BIT(0),
893 .halt_reg = 0xb080,
895 .hwcg_reg = 0xb080,
898 .enable_reg = 0xb080,
899 .enable_mask = BIT(0),
908 .halt_reg = 0x4100c,
910 .hwcg_reg = 0x4100c,
913 .enable_reg = 0x52000,
923 .halt_reg = 0x41008,
926 .enable_reg = 0x52000,
936 .halt_reg = 0x41004,
939 .enable_reg = 0x52000,
949 .halt_reg = 0x502c,
952 .enable_reg = 0x502c,
953 .enable_mask = BIT(0),
968 .halt_reg = 0x48000,
971 .enable_reg = 0x52000,
986 .halt_reg = 0x48008,
989 .enable_reg = 0x48008,
990 .enable_mask = BIT(0),
999 .halt_reg = 0x4452c,
1002 .enable_reg = 0x4452c,
1003 .enable_mask = BIT(0),
1014 .enable_reg = 0x52000,
1030 .enable_reg = 0x52000,
1044 .halt_reg = 0xb024,
1047 .enable_reg = 0xb024,
1048 .enable_mask = BIT(0),
1057 .halt_reg = 0xb084,
1059 .hwcg_reg = 0xb084,
1062 .enable_reg = 0xb084,
1063 .enable_mask = BIT(0),
1072 .halt_reg = 0x64000,
1075 .enable_reg = 0x64000,
1076 .enable_mask = BIT(0),
1090 .halt_reg = 0x65000,
1093 .enable_reg = 0x65000,
1094 .enable_mask = BIT(0),
1108 .halt_reg = 0x66000,
1111 .enable_reg = 0x66000,
1112 .enable_mask = BIT(0),
1128 .enable_reg = 0x52000,
1144 .enable_reg = 0x52000,
1158 .halt_reg = 0x7100c,
1161 .enable_reg = 0x7100c,
1162 .enable_mask = BIT(0),
1171 .halt_reg = 0x71018,
1174 .enable_reg = 0x71018,
1175 .enable_mask = BIT(0),
1184 .halt_reg = 0x4d008,
1187 .enable_reg = 0x4d008,
1188 .enable_mask = BIT(0),
1197 .halt_reg = 0x73008,
1200 .enable_reg = 0x73008,
1201 .enable_mask = BIT(0),
1210 .halt_reg = 0x73018,
1213 .enable_reg = 0x73018,
1214 .enable_mask = BIT(0),
1223 .halt_reg = 0x7301c,
1226 .enable_reg = 0x7301c,
1227 .enable_mask = BIT(0),
1236 .halt_reg = 0x4d004,
1238 .hwcg_reg = 0x4d004,
1241 .enable_reg = 0x4d004,
1242 .enable_mask = BIT(0),
1251 .halt_reg = 0x4d1a0,
1253 .hwcg_reg = 0x4d1a0,
1256 .enable_reg = 0x4d1a0,
1257 .enable_mask = BIT(0),
1268 .enable_reg = 0x52000,
1284 .enable_reg = 0x52000,
1299 .halt_reg = 0x3300c,
1302 .enable_reg = 0x3300c,
1303 .enable_mask = BIT(0),
1317 .halt_reg = 0x33004,
1319 .hwcg_reg = 0x33004,
1322 .enable_reg = 0x33004,
1323 .enable_mask = BIT(0),
1332 .halt_reg = 0x33008,
1335 .enable_reg = 0x33008,
1336 .enable_mask = BIT(0),
1345 .halt_reg = 0x34004,
1347 .hwcg_reg = 0x34004,
1350 .enable_reg = 0x52000,
1360 .halt_reg = 0x4b004,
1362 .hwcg_reg = 0x4b004,
1365 .enable_reg = 0x4b004,
1366 .enable_mask = BIT(0),
1375 .halt_reg = 0x4b008,
1378 .enable_reg = 0x4b008,
1379 .enable_mask = BIT(0),
1393 .halt_reg = 0x17014,
1396 .enable_reg = 0x52008,
1406 .halt_reg = 0x1700c,
1409 .enable_reg = 0x52008,
1419 .halt_reg = 0x17030,
1422 .enable_reg = 0x52008,
1437 .halt_reg = 0x17160,
1440 .enable_reg = 0x52008,
1455 .halt_reg = 0x17290,
1458 .enable_reg = 0x52008,
1473 .halt_reg = 0x173c0,
1476 .enable_reg = 0x52008,
1491 .halt_reg = 0x174f0,
1494 .enable_reg = 0x52008,
1509 .halt_reg = 0x17620,
1512 .enable_reg = 0x52008,
1527 .halt_reg = 0x18004,
1530 .enable_reg = 0x52008,
1540 .halt_reg = 0x18008,
1543 .enable_reg = 0x52008,
1553 .halt_reg = 0x18014,
1556 .enable_reg = 0x52008,
1571 .halt_reg = 0x18144,
1574 .enable_reg = 0x52008,
1589 .halt_reg = 0x18274,
1592 .enable_reg = 0x52008,
1607 .halt_reg = 0x183a4,
1610 .enable_reg = 0x52008,
1625 .halt_reg = 0x184d4,
1628 .enable_reg = 0x52008,
1643 .halt_reg = 0x18604,
1646 .enable_reg = 0x52008,
1661 .halt_reg = 0x17004,
1664 .enable_reg = 0x52008,
1674 .halt_reg = 0x17008,
1676 .hwcg_reg = 0x17008,
1679 .enable_reg = 0x52008,
1689 .halt_reg = 0x1800c,
1692 .enable_reg = 0x52008,
1702 .halt_reg = 0x18010,
1704 .hwcg_reg = 0x18010,
1707 .enable_reg = 0x52008,
1717 .halt_reg = 0x12008,
1720 .enable_reg = 0x12008,
1721 .enable_mask = BIT(0),
1730 .halt_reg = 0x1200c,
1733 .enable_reg = 0x1200c,
1734 .enable_mask = BIT(0),
1748 .halt_reg = 0x12040,
1751 .enable_reg = 0x12040,
1752 .enable_mask = BIT(0),
1766 .halt_reg = 0x14008,
1769 .enable_reg = 0x14008,
1770 .enable_mask = BIT(0),
1779 .halt_reg = 0x14004,
1782 .enable_reg = 0x14004,
1783 .enable_mask = BIT(0),
1798 .halt_reg = 0x4144,
1801 .enable_reg = 0x52000,
1802 .enable_mask = BIT(0),
1816 .halt_reg = 0x8c000,
1819 .enable_reg = 0x8c000,
1820 .enable_mask = BIT(0),
1829 .halt_reg = 0x77014,
1831 .hwcg_reg = 0x77014,
1834 .enable_reg = 0x77014,
1835 .enable_mask = BIT(0),
1844 .halt_reg = 0x77038,
1846 .hwcg_reg = 0x77038,
1849 .enable_reg = 0x77038,
1850 .enable_mask = BIT(0),
1864 .halt_reg = 0x77090,
1866 .hwcg_reg = 0x77090,
1869 .enable_reg = 0x77090,
1870 .enable_mask = BIT(0),
1884 .halt_reg = 0x77094,
1886 .hwcg_reg = 0x77094,
1889 .enable_reg = 0x77094,
1890 .enable_mask = BIT(0),
1904 .halt_reg = 0x7701c,
1907 .enable_reg = 0x7701c,
1908 .enable_mask = BIT(0),
1917 .halt_reg = 0x77018,
1920 .enable_reg = 0x77018,
1921 .enable_mask = BIT(0),
1930 .halt_reg = 0x7708c,
1932 .hwcg_reg = 0x7708c,
1935 .enable_reg = 0x7708c,
1936 .enable_mask = BIT(0),
1950 .halt_reg = 0xf010,
1953 .enable_reg = 0xf010,
1954 .enable_mask = BIT(0),
1968 .halt_reg = 0xf018,
1971 .enable_reg = 0xf018,
1972 .enable_mask = BIT(0),
1986 .halt_reg = 0xf014,
1989 .enable_reg = 0xf014,
1990 .enable_mask = BIT(0),
1999 .halt_reg = 0x8c010,
2002 .enable_reg = 0x8c010,
2003 .enable_mask = BIT(0),
2012 .halt_reg = 0xf050,
2015 .enable_reg = 0xf050,
2016 .enable_mask = BIT(0),
2030 .halt_reg = 0xf054,
2033 .enable_reg = 0xf054,
2034 .enable_mask = BIT(0),
2048 .halt_reg = 0xf058,
2051 .enable_reg = 0xf058,
2052 .enable_mask = BIT(0),
2061 .halt_reg = 0x6a004,
2063 .hwcg_reg = 0x6a004,
2066 .enable_reg = 0x6a004,
2067 .enable_mask = BIT(0),
2076 .halt_reg = 0xb01c,
2079 .enable_reg = 0xb01c,
2080 .enable_mask = BIT(0),
2091 .enable_reg = 0x52000,
2106 .halt_reg = 0xb07c,
2108 .hwcg_reg = 0xb07c,
2111 .enable_reg = 0xb07c,
2112 .enable_mask = BIT(0),
2121 .halt_reg = 0x8a000,
2124 .enable_reg = 0x8a000,
2125 .enable_mask = BIT(0),
2134 .halt_reg = 0x8a004,
2137 .enable_reg = 0x8a004,
2138 .enable_mask = BIT(0),
2147 .halt_reg = 0x8a00c,
2150 .enable_reg = 0x8a00c,
2151 .enable_mask = BIT(0),
2160 .halt_reg = 0x8a150,
2163 .enable_reg = 0x8a150,
2164 .enable_mask = BIT(0),
2173 .halt_reg = 0x8a154,
2176 .enable_reg = 0x8a154,
2177 .enable_mask = BIT(0),
2186 .halt_reg = 0x47018,
2189 .enable_reg = 0x47018,
2190 .enable_mask = BIT(0),
2199 .gdscr = 0x77004,
2207 .gdscr = 0x0f004,
2215 .gdscr = 0x7d040,
2224 .gdscr = 0x7d044,
2375 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2376 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2377 [GCC_UFS_PHY_BCR] = { 0x77000 },
2378 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2379 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2380 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2381 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2382 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2383 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2384 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2385 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2407 .max_register = 0x18208c,
2442 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sc7180_probe()
2443 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sc7180_probe()
2444 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sc7180_probe()
2447 qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ in gcc_sc7180_probe()
2448 qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ in gcc_sc7180_probe()
2449 qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ in gcc_sc7180_probe()
2450 qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ in gcc_sc7180_probe()
2451 qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ in gcc_sc7180_probe()
2452 qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ in gcc_sc7180_probe()
2453 qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ in gcc_sc7180_probe()
2454 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sc7180_probe()