Lines Matching +full:0 +full:x0c08
33 .offset = 0,
36 .enable_reg = 0x1480,
37 .enable_mask = BIT(0),
50 .offset = 0,
63 .offset = 0x1dc0,
66 .enable_reg = 0x1480,
80 .offset = 0x1dc0,
94 { P_XO, 0 },
104 { P_XO, 0 },
116 F(50000000, P_GPLL0, 12, 0, 0),
117 F(100000000, P_GPLL0, 6, 0, 0),
118 F(150000000, P_GPLL0, 4, 0, 0),
119 F(171430000, P_GPLL0, 3.5, 0, 0),
120 F(200000000, P_GPLL0, 3, 0, 0),
121 F(240000000, P_GPLL0, 2.5, 0, 0),
126 .cmd_rcgr = 0x1d68,
140 F(19200000, P_XO, 1, 0, 0),
146 .cmd_rcgr = 0x03d4,
160 F(19200000, P_XO, 1, 0, 0),
161 F(50000000, P_GPLL0, 12, 0, 0),
166 .cmd_rcgr = 0x0660,
180 F(4800000, P_XO, 4, 0, 0),
181 F(9600000, P_XO, 2, 0, 0),
183 F(19200000, P_XO, 1, 0, 0),
186 F(48000000, P_GPLL0, 12.5, 0, 0),
187 F(50000000, P_GPLL0, 12, 0, 0),
193 F(4800000, P_XO, 4, 0, 0),
194 F(9600000, P_XO, 2, 0, 0),
196 F(19200000, P_XO, 1, 0, 0),
198 F(50000000, P_GPLL0, 12, 0, 0),
203 .cmd_rcgr = 0x064c,
217 .cmd_rcgr = 0x06e0,
231 F(4800000, P_XO, 4, 0, 0),
232 F(9600000, P_XO, 2, 0, 0),
234 F(19200000, P_XO, 1, 0, 0),
237 F(42860000, P_GPLL0, 14, 0, 0),
238 F(46150000, P_GPLL0, 13, 0, 0),
243 .cmd_rcgr = 0x06cc,
257 .cmd_rcgr = 0x0760,
271 F(4800000, P_XO, 4, 0, 0),
272 F(9600000, P_XO, 2, 0, 0),
274 F(19200000, P_XO, 1, 0, 0),
277 F(42860000, P_GPLL0, 14, 0, 0),
278 F(44440000, P_GPLL0, 13.5, 0, 0),
283 .cmd_rcgr = 0x074c,
297 .cmd_rcgr = 0x07e0,
310 .cmd_rcgr = 0x07cc,
324 .cmd_rcgr = 0x0860,
338 F(4800000, P_XO, 4, 0, 0),
339 F(9600000, P_XO, 2, 0, 0),
341 F(19200000, P_XO, 1, 0, 0),
344 F(40000000, P_GPLL0, 15, 0, 0),
345 F(42860000, P_GPLL0, 14, 0, 0),
350 .cmd_rcgr = 0x084c,
364 .cmd_rcgr = 0x08e0,
378 F(4800000, P_XO, 4, 0, 0),
379 F(9600000, P_XO, 2, 0, 0),
381 F(19200000, P_XO, 1, 0, 0),
384 F(41380000, P_GPLL0, 15, 0, 0),
385 F(42860000, P_GPLL0, 14, 0, 0),
390 .cmd_rcgr = 0x08cc,
408 F(19200000, P_XO, 1, 0, 0),
411 F(40000000, P_GPLL0, 15, 0, 0),
413 F(48000000, P_GPLL0, 12.5, 0, 0),
417 F(60000000, P_GPLL0, 10, 0, 0),
418 F(63160000, P_GPLL0, 9.5, 0, 0),
423 .cmd_rcgr = 0x068c,
437 .cmd_rcgr = 0x070c,
451 .cmd_rcgr = 0x078c,
465 .cmd_rcgr = 0x080c,
479 .cmd_rcgr = 0x088c,
493 .cmd_rcgr = 0x090c,
507 .cmd_rcgr = 0x09a0,
521 F(4800000, P_XO, 4, 0, 0),
522 F(9600000, P_XO, 2, 0, 0),
524 F(19200000, P_XO, 1, 0, 0),
527 F(42860000, P_GPLL0, 14, 0, 0),
528 F(44440000, P_GPLL0, 13.5, 0, 0),
533 .cmd_rcgr = 0x098c,
547 .cmd_rcgr = 0x0a20,
560 .cmd_rcgr = 0x0a0c,
575 F(4800000, P_XO, 4, 0, 0),
576 F(9600000, P_XO, 2, 0, 0),
578 F(19200000, P_XO, 1, 0, 0),
581 F(42860000, P_GPLL0, 14, 0, 0),
582 F(48000000, P_GPLL0, 12.5, 0, 0),
587 .cmd_rcgr = 0x0aa0,
600 .cmd_rcgr = 0x0a8c,
614 .cmd_rcgr = 0x0b20,
627 .cmd_rcgr = 0x0b0c,
641 .cmd_rcgr = 0x0ba0,
654 .cmd_rcgr = 0x0b8c,
669 .cmd_rcgr = 0x0c20,
683 F(4800000, P_XO, 4, 0, 0),
684 F(9600000, P_XO, 2, 0, 0),
686 F(19200000, P_XO, 1, 0, 0),
689 F(44440000, P_GPLL0, 13.5, 0, 0),
690 F(48000000, P_GPLL0, 12.5, 0, 0),
695 .cmd_rcgr = 0x0c0c,
709 .cmd_rcgr = 0x09cc,
723 .cmd_rcgr = 0x0a4c,
737 .cmd_rcgr = 0x0acc,
751 .cmd_rcgr = 0x0b4c,
765 .cmd_rcgr = 0x0bcc,
779 .cmd_rcgr = 0x0c4c,
793 F(19200000, P_XO, 1, 0, 0),
794 F(100000000, P_GPLL0, 6, 0, 0),
795 F(200000000, P_GPLL0, 3, 0, 0),
800 .cmd_rcgr = 0x1904,
814 F(19200000, P_XO, 1, 0, 0),
815 F(100000000, P_GPLL0, 6, 0, 0),
816 F(200000000, P_GPLL0, 3, 0, 0),
821 .cmd_rcgr = 0x1944,
835 F(19200000, P_XO, 1, 0, 0),
836 F(100000000, P_GPLL0, 6, 0, 0),
837 F(200000000, P_GPLL0, 3, 0, 0),
842 .cmd_rcgr = 0x1984,
861 .cmd_rcgr = 0x1b00,
876 F(125000000, P_XO, 1, 0, 0),
881 .cmd_rcgr = 0x1adc,
900 .cmd_rcgr = 0x1b80,
915 .cmd_rcgr = 0x1b5c,
929 F(60000000, P_GPLL0, 10, 0, 0),
934 .cmd_rcgr = 0x0cd0,
951 F(50000000, P_GPLL0, 12, 0, 0),
952 F(100000000, P_GPLL0, 6, 0, 0),
953 F(192000000, P_GPLL4, 2, 0, 0),
954 F(384000000, P_GPLL4, 1, 0, 0),
963 F(50000000, P_GPLL0, 12, 0, 0),
964 F(100000000, P_GPLL0, 6, 0, 0),
965 F(172000000, P_GPLL4, 2, 0, 0),
966 F(344000000, P_GPLL4, 1, 0, 0),
971 .cmd_rcgr = 0x04d0,
989 F(50000000, P_GPLL0, 12, 0, 0),
990 F(100000000, P_GPLL0, 6, 0, 0),
991 F(200000000, P_GPLL0, 3, 0, 0),
996 .cmd_rcgr = 0x0510,
1010 .cmd_rcgr = 0x0550,
1024 .cmd_rcgr = 0x0590,
1043 .cmd_rcgr = 0x0d90,
1058 F(19200000, P_XO, 1, 0, 0),
1059 F(60000000, P_GPLL0, 10, 0, 0),
1064 .cmd_rcgr = 0x03e8,
1077 F(1200000, P_XO, 16, 0, 0),
1082 .cmd_rcgr = 0x1414,
1096 F(75000000, P_GPLL0, 8, 0, 0),
1101 .cmd_rcgr = 0x0490,
1114 .halt_reg = 0x05c4,
1117 .enable_reg = 0x1484,
1127 .halt_reg = 0x0648,
1129 .enable_reg = 0x0648,
1130 .enable_mask = BIT(0),
1142 .halt_reg = 0x0644,
1144 .enable_reg = 0x0644,
1145 .enable_mask = BIT(0),
1157 .halt_reg = 0x06c8,
1159 .enable_reg = 0x06c8,
1160 .enable_mask = BIT(0),
1172 .halt_reg = 0x06c4,
1174 .enable_reg = 0x06c4,
1175 .enable_mask = BIT(0),
1187 .halt_reg = 0x0748,
1189 .enable_reg = 0x0748,
1190 .enable_mask = BIT(0),
1202 .halt_reg = 0x0744,
1204 .enable_reg = 0x0744,
1205 .enable_mask = BIT(0),
1217 .halt_reg = 0x07c8,
1219 .enable_reg = 0x07c8,
1220 .enable_mask = BIT(0),
1232 .halt_reg = 0x07c4,
1234 .enable_reg = 0x07c4,
1235 .enable_mask = BIT(0),
1247 .halt_reg = 0x0848,
1249 .enable_reg = 0x0848,
1250 .enable_mask = BIT(0),
1262 .halt_reg = 0x0844,
1264 .enable_reg = 0x0844,
1265 .enable_mask = BIT(0),
1277 .halt_reg = 0x08c8,
1279 .enable_reg = 0x08c8,
1280 .enable_mask = BIT(0),
1292 .halt_reg = 0x08c4,
1294 .enable_reg = 0x08c4,
1295 .enable_mask = BIT(0),
1307 .halt_reg = 0x0684,
1309 .enable_reg = 0x0684,
1310 .enable_mask = BIT(0),
1322 .halt_reg = 0x0704,
1324 .enable_reg = 0x0704,
1325 .enable_mask = BIT(0),
1337 .halt_reg = 0x0784,
1339 .enable_reg = 0x0784,
1340 .enable_mask = BIT(0),
1352 .halt_reg = 0x0804,
1354 .enable_reg = 0x0804,
1355 .enable_mask = BIT(0),
1367 .halt_reg = 0x0884,
1369 .enable_reg = 0x0884,
1370 .enable_mask = BIT(0),
1382 .halt_reg = 0x0904,
1384 .enable_reg = 0x0904,
1385 .enable_mask = BIT(0),
1397 .halt_reg = 0x0944,
1400 .enable_reg = 0x1484,
1410 .halt_reg = 0x0988,
1412 .enable_reg = 0x0988,
1413 .enable_mask = BIT(0),
1425 .halt_reg = 0x0984,
1427 .enable_reg = 0x0984,
1428 .enable_mask = BIT(0),
1440 .halt_reg = 0x0a08,
1442 .enable_reg = 0x0a08,
1443 .enable_mask = BIT(0),
1455 .halt_reg = 0x0a04,
1457 .enable_reg = 0x0a04,
1458 .enable_mask = BIT(0),
1470 .halt_reg = 0x0a88,
1472 .enable_reg = 0x0a88,
1473 .enable_mask = BIT(0),
1485 .halt_reg = 0x0a84,
1487 .enable_reg = 0x0a84,
1488 .enable_mask = BIT(0),
1500 .halt_reg = 0x0b08,
1502 .enable_reg = 0x0b08,
1503 .enable_mask = BIT(0),
1515 .halt_reg = 0x0b04,
1517 .enable_reg = 0x0b04,
1518 .enable_mask = BIT(0),
1530 .halt_reg = 0x0b88,
1532 .enable_reg = 0x0b88,
1533 .enable_mask = BIT(0),
1545 .halt_reg = 0x0b84,
1547 .enable_reg = 0x0b84,
1548 .enable_mask = BIT(0),
1560 .halt_reg = 0x0c08,
1562 .enable_reg = 0x0c08,
1563 .enable_mask = BIT(0),
1575 .halt_reg = 0x0c04,
1577 .enable_reg = 0x0c04,
1578 .enable_mask = BIT(0),
1590 .halt_reg = 0x09c4,
1592 .enable_reg = 0x09c4,
1593 .enable_mask = BIT(0),
1605 .halt_reg = 0x0a44,
1607 .enable_reg = 0x0a44,
1608 .enable_mask = BIT(0),
1620 .halt_reg = 0x0ac4,
1622 .enable_reg = 0x0ac4,
1623 .enable_mask = BIT(0),
1635 .halt_reg = 0x0b44,
1637 .enable_reg = 0x0b44,
1638 .enable_mask = BIT(0),
1650 .halt_reg = 0x0bc4,
1652 .enable_reg = 0x0bc4,
1653 .enable_mask = BIT(0),
1665 .halt_reg = 0x0c44,
1667 .enable_reg = 0x0c44,
1668 .enable_mask = BIT(0),
1680 .halt_reg = 0x1900,
1682 .enable_reg = 0x1900,
1683 .enable_mask = BIT(0),
1695 .halt_reg = 0x1940,
1697 .enable_reg = 0x1940,
1698 .enable_mask = BIT(0),
1710 .halt_reg = 0x1980,
1712 .enable_reg = 0x1980,
1713 .enable_mask = BIT(0),
1725 .halt_reg = 0x0280,
1727 .enable_reg = 0x0280,
1728 .enable_mask = BIT(0),
1737 .halt_reg = 0x0284,
1739 .enable_reg = 0x0284,
1740 .enable_mask = BIT(0),
1749 .halt_reg = 0x1ad4,
1751 .enable_reg = 0x1ad4,
1752 .enable_mask = BIT(0),
1764 .halt_reg = 0x1ad0,
1766 .enable_reg = 0x1ad0,
1767 .enable_mask = BIT(0),
1776 .halt_reg = 0x1acc,
1778 .enable_reg = 0x1acc,
1779 .enable_mask = BIT(0),
1788 .halt_reg = 0x1ad8,
1791 .enable_reg = 0x1ad8,
1792 .enable_mask = BIT(0),
1804 .halt_reg = 0x1ac8,
1807 .enable_reg = 0x1ac8,
1808 .enable_mask = BIT(0),
1817 .halt_reg = 0x1b54,
1819 .enable_reg = 0x1b54,
1820 .enable_mask = BIT(0),
1832 .halt_reg = 0x1b54,
1834 .enable_reg = 0x1b54,
1835 .enable_mask = BIT(0),
1844 .halt_reg = 0x1b50,
1846 .enable_reg = 0x1b50,
1847 .enable_mask = BIT(0),
1856 .halt_reg = 0x1b58,
1859 .enable_reg = 0x1b58,
1860 .enable_mask = BIT(0),
1872 .halt_reg = 0x1b48,
1874 .enable_reg = 0x1b48,
1875 .enable_mask = BIT(0),
1884 .halt_reg = 0x0ccc,
1886 .enable_reg = 0x0ccc,
1887 .enable_mask = BIT(0),
1899 .halt_reg = 0x0cc4,
1901 .enable_reg = 0x0cc4,
1902 .enable_mask = BIT(0),
1911 .halt_reg = 0x04c4,
1913 .enable_reg = 0x04c4,
1914 .enable_mask = BIT(0),
1926 .halt_reg = 0x04c8,
1928 .enable_reg = 0x04c8,
1929 .enable_mask = BIT(0),
1938 .halt_reg = 0x0508,
1940 .enable_reg = 0x0508,
1941 .enable_mask = BIT(0),
1950 .halt_reg = 0x0504,
1952 .enable_reg = 0x0504,
1953 .enable_mask = BIT(0),
1965 .halt_reg = 0x0548,
1967 .enable_reg = 0x0548,
1968 .enable_mask = BIT(0),
1977 .halt_reg = 0x0544,
1979 .enable_reg = 0x0544,
1980 .enable_mask = BIT(0),
1992 .halt_reg = 0x0588,
1994 .enable_reg = 0x0588,
1995 .enable_mask = BIT(0),
2004 .halt_reg = 0x0584,
2006 .enable_reg = 0x0584,
2007 .enable_mask = BIT(0),
2019 .halt_reg = 0x1d7c,
2021 .enable_reg = 0x1d7c,
2022 .enable_mask = BIT(0),
2034 .halt_reg = 0x03fc,
2036 .enable_reg = 0x03fc,
2037 .enable_mask = BIT(0),
2049 .halt_reg = 0x0d84,
2051 .enable_reg = 0x0d84,
2052 .enable_mask = BIT(0),
2061 .halt_reg = 0x0d88,
2063 .enable_reg = 0x0d88,
2064 .enable_mask = BIT(0),
2076 .halt_reg = 0x1d4c,
2078 .enable_reg = 0x1d4c,
2079 .enable_mask = BIT(0),
2088 .halt_reg = 0x1d48,
2090 .enable_reg = 0x1d48,
2091 .enable_mask = BIT(0),
2103 .halt_reg = 0x1d54,
2105 .enable_reg = 0x1d54,
2106 .enable_mask = BIT(0),
2118 .halt_reg = 0x1d60,
2121 .enable_reg = 0x1d60,
2122 .enable_mask = BIT(0),
2131 .halt_reg = 0x1d64,
2134 .enable_reg = 0x1d64,
2135 .enable_mask = BIT(0),
2144 .halt_reg = 0x1d50,
2146 .enable_reg = 0x1d50,
2147 .enable_mask = BIT(0),
2159 .halt_reg = 0x1d58,
2162 .enable_reg = 0x1d58,
2163 .enable_mask = BIT(0),
2172 .halt_reg = 0x1d5c,
2175 .enable_reg = 0x1d5c,
2176 .enable_mask = BIT(0),
2185 .halt_reg = 0x04ac,
2187 .enable_reg = 0x04ac,
2188 .enable_mask = BIT(0),
2202 .halt_reg = 0x03c8,
2204 .enable_reg = 0x03c8,
2205 .enable_mask = BIT(0),
2217 .halt_reg = 0x03d0,
2219 .enable_reg = 0x03d0,
2220 .enable_mask = BIT(0),
2232 .halt_reg = 0x03cc,
2234 .enable_reg = 0x03cc,
2235 .enable_mask = BIT(0),
2249 .halt_reg = 0x1408,
2251 .enable_reg = 0x1408,
2252 .enable_mask = BIT(0),
2264 .halt_reg = 0x140c,
2267 .enable_reg = 0x140c,
2268 .enable_mask = BIT(0),
2277 .halt_reg = 0x0488,
2279 .enable_reg = 0x0488,
2280 .enable_mask = BIT(0),
2289 .halt_reg = 0x0484,
2291 .enable_reg = 0x0484,
2292 .enable_mask = BIT(0),
2304 .halt_reg = 0x1a84,
2306 .enable_reg = 0x1a84,
2307 .enable_mask = BIT(0),
2318 .enable_reg = 0x1484,
2332 .enable_reg = 0x1484,
2344 .halt_reg = 0x1e00,
2347 .enable_reg = 0x1E00,
2348 .enable_mask = BIT(0),
2357 .halt_reg = 0x1e04,
2360 .enable_reg = 0x1E04,
2361 .enable_mask = BIT(0),
2370 .halt_reg = 0x1e0c,
2373 .enable_reg = 0x1E0C,
2374 .enable_mask = BIT(0),
2383 .halt_reg = 0x1e08,
2386 .enable_reg = 0x1E08,
2387 .enable_mask = BIT(0),
2396 .halt_reg = 0x0e04,
2398 .hwcg_reg = 0x0e04,
2401 .enable_reg = 0x1484,
2411 .halt_reg = 0x0d04,
2414 .enable_reg = 0x1484,
2424 .gdscr = 0x1ac4,
2432 .gdscr = 0x1b44,
2440 .gdscr = 0x3c4,
2448 .gdscr = 0x1d44,
2627 [USB3_PHY_RESET] = { 0x1400 },
2628 [USB3PHY_PHY_RESET] = { 0x1404 },
2629 [MSS_RESET] = { 0x1680 },
2630 [PCIE_PHY_0_RESET] = { 0x1b18 },
2631 [PCIE_PHY_1_RESET] = { 0x1b98 },
2632 [QUSB2_PHY_RESET] = { 0x04b8 },
2639 .max_register = 0x2000,