Lines Matching +full:0 +full:x0c08
36 .l_reg = 0x0004,
37 .m_reg = 0x0008,
38 .n_reg = 0x000c,
39 .config_reg = 0x0014,
40 .mode_reg = 0x0000,
41 .status_reg = 0x001c,
54 .enable_reg = 0x1480,
55 .enable_mask = BIT(0),
67 .l_reg = 0x1dc4,
68 .m_reg = 0x1dc8,
69 .n_reg = 0x1dcc,
70 .config_reg = 0x1dd4,
71 .mode_reg = 0x1dc0,
72 .status_reg = 0x1ddc,
85 .enable_reg = 0x1480,
98 { P_XO, 0 },
108 { P_XO, 0 },
120 .cmd_rcgr = 0x0150,
132 .cmd_rcgr = 0x0190,
144 .cmd_rcgr = 0x0120,
156 .l_reg = 0x0044,
157 .m_reg = 0x0048,
158 .n_reg = 0x004c,
159 .config_reg = 0x0054,
160 .mode_reg = 0x0040,
161 .status_reg = 0x005c,
174 .enable_reg = 0x1480,
192 .cmd_rcgr = 0x03d4,
206 F(19200000, P_XO, 1, 0, 0),
207 F(37500000, P_GPLL0, 16, 0, 0),
208 F(50000000, P_GPLL0, 12, 0, 0),
213 .cmd_rcgr = 0x0660,
227 F(4800000, P_XO, 4, 0, 0),
228 F(9600000, P_XO, 2, 0, 0),
230 F(19200000, P_XO, 1, 0, 0),
232 F(50000000, P_GPLL0, 12, 0, 0),
237 .cmd_rcgr = 0x064c,
251 .cmd_rcgr = 0x06e0,
264 .cmd_rcgr = 0x06cc,
278 .cmd_rcgr = 0x0760,
291 .cmd_rcgr = 0x074c,
305 .cmd_rcgr = 0x07e0,
318 .cmd_rcgr = 0x07cc,
332 .cmd_rcgr = 0x0860,
345 .cmd_rcgr = 0x084c,
359 .cmd_rcgr = 0x08e0,
372 .cmd_rcgr = 0x08cc,
390 F(19200000, P_XO, 1, 0, 0),
393 F(40000000, P_GPLL0, 15, 0, 0),
395 F(48000000, P_GPLL0, 12.5, 0, 0),
399 F(60000000, P_GPLL0, 10, 0, 0),
400 F(63160000, P_GPLL0, 9.5, 0, 0),
405 .cmd_rcgr = 0x068c,
419 .cmd_rcgr = 0x070c,
433 .cmd_rcgr = 0x078c,
447 .cmd_rcgr = 0x080c,
461 .cmd_rcgr = 0x088c,
475 .cmd_rcgr = 0x090c,
489 .cmd_rcgr = 0x09a0,
502 .cmd_rcgr = 0x098c,
516 .cmd_rcgr = 0x0a20,
529 .cmd_rcgr = 0x0a0c,
543 .cmd_rcgr = 0x0aa0,
556 .cmd_rcgr = 0x0a8c,
570 .cmd_rcgr = 0x0b20,
583 .cmd_rcgr = 0x0b0c,
597 .cmd_rcgr = 0x0ba0,
610 .cmd_rcgr = 0x0b8c,
624 .cmd_rcgr = 0x0c20,
637 .cmd_rcgr = 0x0c0c,
651 .cmd_rcgr = 0x09cc,
665 .cmd_rcgr = 0x0a4c,
679 .cmd_rcgr = 0x0acc,
693 .cmd_rcgr = 0x0b4c,
707 .cmd_rcgr = 0x0bcc,
721 .cmd_rcgr = 0x0c4c,
735 F(50000000, P_GPLL0, 12, 0, 0),
736 F(100000000, P_GPLL0, 6, 0, 0),
741 F(50000000, P_GPLL0, 12, 0, 0),
742 F(75000000, P_GPLL0, 8, 0, 0),
743 F(100000000, P_GPLL0, 6, 0, 0),
744 F(150000000, P_GPLL0, 4, 0, 0),
749 .cmd_rcgr = 0x1050,
762 F(50000000, P_GPLL0, 12, 0, 0),
763 F(75000000, P_GPLL0, 8, 0, 0),
764 F(100000000, P_GPLL0, 6, 0, 0),
765 F(150000000, P_GPLL0, 4, 0, 0),
770 .cmd_rcgr = 0x1090,
783 F(19200000, P_XO, 1, 0, 0),
788 F(4800000, P_XO, 4, 0, 0),
792 F(9600000, P_XO, 2, 0, 0),
794 F(19200000, P_XO, 1, 0, 0),
801 .cmd_rcgr = 0x1904,
815 .cmd_rcgr = 0x1944,
829 .cmd_rcgr = 0x1984,
843 F(60000000, P_GPLL0, 10, 0, 0),
848 .cmd_rcgr = 0x0cd0,
865 F(50000000, P_GPLL0, 12, 0, 0),
866 F(100000000, P_GPLL0, 6, 0, 0),
867 F(200000000, P_GPLL0, 3, 0, 0),
876 F(50000000, P_GPLL0, 12, 0, 0),
877 F(100000000, P_GPLL0, 6, 0, 0),
878 F(192000000, P_GPLL4, 4, 0, 0),
879 F(200000000, P_GPLL0, 3, 0, 0),
880 F(384000000, P_GPLL4, 2, 0, 0),
892 .cmd_rcgr = 0x04d0,
901 .cmd_rcgr = 0x0510,
915 .cmd_rcgr = 0x0550,
929 .cmd_rcgr = 0x0590,
948 .cmd_rcgr = 0x0d90,
962 F(60000000, P_GPLL0, 10, 0, 0),
967 .cmd_rcgr = 0x03e8,
980 F(60000000, P_GPLL0, 10, 0, 0),
981 F(75000000, P_GPLL0, 8, 0, 0),
986 .cmd_rcgr = 0x0490,
999 F(480000000, P_GPLL1, 1, 0, 0),
1004 { P_XO, 0 },
1009 .cmd_rcgr = 0x0440,
1025 F(9600000, P_XO, 2, 0, 0),
1030 .cmd_rcgr = 0x0458,
1043 F(60000000, P_GPLL0, 10, 0, 0),
1044 F(75000000, P_GPLL0, 8, 0, 0),
1049 .cmd_rcgr = 0x041c,
1062 .enable_reg = 0x1484,
1075 .halt_reg = 0x0d44,
1078 .enable_reg = 0x1484,
1092 .halt_reg = 0x05c4,
1095 .enable_reg = 0x1484,
1109 .halt_reg = 0x0648,
1111 .enable_reg = 0x0648,
1112 .enable_mask = BIT(0),
1126 .halt_reg = 0x0644,
1128 .enable_reg = 0x0644,
1129 .enable_mask = BIT(0),
1143 .halt_reg = 0x06c8,
1145 .enable_reg = 0x06c8,
1146 .enable_mask = BIT(0),
1160 .halt_reg = 0x06c4,
1162 .enable_reg = 0x06c4,
1163 .enable_mask = BIT(0),
1177 .halt_reg = 0x0748,
1179 .enable_reg = 0x0748,
1180 .enable_mask = BIT(0),
1194 .halt_reg = 0x0744,
1196 .enable_reg = 0x0744,
1197 .enable_mask = BIT(0),
1211 .halt_reg = 0x07c8,
1213 .enable_reg = 0x07c8,
1214 .enable_mask = BIT(0),
1228 .halt_reg = 0x07c4,
1230 .enable_reg = 0x07c4,
1231 .enable_mask = BIT(0),
1245 .halt_reg = 0x0848,
1247 .enable_reg = 0x0848,
1248 .enable_mask = BIT(0),
1262 .halt_reg = 0x0844,
1264 .enable_reg = 0x0844,
1265 .enable_mask = BIT(0),
1279 .halt_reg = 0x08c8,
1281 .enable_reg = 0x08c8,
1282 .enable_mask = BIT(0),
1296 .halt_reg = 0x08c4,
1298 .enable_reg = 0x08c4,
1299 .enable_mask = BIT(0),
1313 .halt_reg = 0x0684,
1315 .enable_reg = 0x0684,
1316 .enable_mask = BIT(0),
1330 .halt_reg = 0x0704,
1332 .enable_reg = 0x0704,
1333 .enable_mask = BIT(0),
1347 .halt_reg = 0x0784,
1349 .enable_reg = 0x0784,
1350 .enable_mask = BIT(0),
1364 .halt_reg = 0x0804,
1366 .enable_reg = 0x0804,
1367 .enable_mask = BIT(0),
1381 .halt_reg = 0x0884,
1383 .enable_reg = 0x0884,
1384 .enable_mask = BIT(0),
1398 .halt_reg = 0x0904,
1400 .enable_reg = 0x0904,
1401 .enable_mask = BIT(0),
1415 .halt_reg = 0x0944,
1418 .enable_reg = 0x1484,
1432 .halt_reg = 0x0988,
1434 .enable_reg = 0x0988,
1435 .enable_mask = BIT(0),
1449 .halt_reg = 0x0984,
1451 .enable_reg = 0x0984,
1452 .enable_mask = BIT(0),
1466 .halt_reg = 0x0a08,
1468 .enable_reg = 0x0a08,
1469 .enable_mask = BIT(0),
1483 .halt_reg = 0x0a04,
1485 .enable_reg = 0x0a04,
1486 .enable_mask = BIT(0),
1500 .halt_reg = 0x0a88,
1502 .enable_reg = 0x0a88,
1503 .enable_mask = BIT(0),
1517 .halt_reg = 0x0a84,
1519 .enable_reg = 0x0a84,
1520 .enable_mask = BIT(0),
1534 .halt_reg = 0x0b08,
1536 .enable_reg = 0x0b08,
1537 .enable_mask = BIT(0),
1551 .halt_reg = 0x0b04,
1553 .enable_reg = 0x0b04,
1554 .enable_mask = BIT(0),
1568 .halt_reg = 0x0b88,
1570 .enable_reg = 0x0b88,
1571 .enable_mask = BIT(0),
1585 .halt_reg = 0x0b84,
1587 .enable_reg = 0x0b84,
1588 .enable_mask = BIT(0),
1602 .halt_reg = 0x0c08,
1604 .enable_reg = 0x0c08,
1605 .enable_mask = BIT(0),
1619 .halt_reg = 0x0c04,
1621 .enable_reg = 0x0c04,
1622 .enable_mask = BIT(0),
1636 .halt_reg = 0x09c4,
1638 .enable_reg = 0x09c4,
1639 .enable_mask = BIT(0),
1653 .halt_reg = 0x0a44,
1655 .enable_reg = 0x0a44,
1656 .enable_mask = BIT(0),
1670 .halt_reg = 0x0ac4,
1672 .enable_reg = 0x0ac4,
1673 .enable_mask = BIT(0),
1687 .halt_reg = 0x0b44,
1689 .enable_reg = 0x0b44,
1690 .enable_mask = BIT(0),
1704 .halt_reg = 0x0bc4,
1706 .enable_reg = 0x0bc4,
1707 .enable_mask = BIT(0),
1721 .halt_reg = 0x0c44,
1723 .enable_reg = 0x0c44,
1724 .enable_mask = BIT(0),
1738 .halt_reg = 0x0e04,
1741 .enable_reg = 0x1484,
1755 .halt_reg = 0x104c,
1758 .enable_reg = 0x1484,
1772 .halt_reg = 0x1048,
1775 .enable_reg = 0x1484,
1789 .halt_reg = 0x1050,
1792 .enable_reg = 0x1484,
1807 .halt_reg = 0x108c,
1810 .enable_reg = 0x1484,
1811 .enable_mask = BIT(0),
1824 .halt_reg = 0x1088,
1827 .enable_reg = 0x1484,
1841 .halt_reg = 0x1090,
1844 .enable_reg = 0x1484,
1859 .halt_reg = 0x1900,
1861 .enable_reg = 0x1900,
1862 .enable_mask = BIT(0),
1876 .halt_reg = 0x1940,
1878 .enable_reg = 0x1940,
1879 .enable_mask = BIT(0),
1893 .halt_reg = 0x1980,
1895 .enable_reg = 0x1980,
1896 .enable_mask = BIT(0),
1910 .halt_reg = 0x11c0,
1912 .enable_reg = 0x11c0,
1913 .enable_mask = BIT(0),
1926 .halt_reg = 0x024c,
1928 .enable_reg = 0x024c,
1929 .enable_mask = BIT(0),
1943 .halt_reg = 0x0248,
1945 .enable_reg = 0x0248,
1946 .enable_mask = BIT(0),
1959 .halt_reg = 0x0280,
1961 .enable_reg = 0x0280,
1962 .enable_mask = BIT(0),
1975 .halt_reg = 0x0284,
1977 .enable_reg = 0x0284,
1978 .enable_mask = BIT(0),
1991 .halt_reg = 0x0ccc,
1993 .enable_reg = 0x0ccc,
1994 .enable_mask = BIT(0),
2008 .halt_reg = 0x0cc4,
2010 .enable_reg = 0x0cc4,
2011 .enable_mask = BIT(0),
2024 .halt_reg = 0x0cc8,
2026 .enable_reg = 0x0cc8,
2027 .enable_mask = BIT(0),
2040 .halt_reg = 0x0d04,
2043 .enable_reg = 0x1484,
2057 .halt_reg = 0x04c8,
2059 .enable_reg = 0x04c8,
2060 .enable_mask = BIT(0),
2073 .halt_reg = 0x04c4,
2075 .enable_reg = 0x04c4,
2076 .enable_mask = BIT(0),
2090 .halt_reg = 0x04e8,
2092 .enable_reg = 0x04e8,
2093 .enable_mask = BIT(0),
2106 .halt_reg = 0x04e4,
2108 .enable_reg = 0x04e4,
2109 .enable_mask = BIT(0),
2122 .halt_reg = 0x0508,
2124 .enable_reg = 0x0508,
2125 .enable_mask = BIT(0),
2138 .halt_reg = 0x0504,
2140 .enable_reg = 0x0504,
2141 .enable_mask = BIT(0),
2155 .halt_reg = 0x0548,
2157 .enable_reg = 0x0548,
2158 .enable_mask = BIT(0),
2171 .halt_reg = 0x0544,
2173 .enable_reg = 0x0544,
2174 .enable_mask = BIT(0),
2188 .halt_reg = 0x0588,
2190 .enable_reg = 0x0588,
2191 .enable_mask = BIT(0),
2204 .halt_reg = 0x0584,
2206 .enable_reg = 0x0584,
2207 .enable_mask = BIT(0),
2221 .halt_reg = 0x0108,
2223 .enable_reg = 0x0108,
2224 .enable_mask = BIT(0),
2238 .halt_reg = 0x0d84,
2240 .enable_reg = 0x0d84,
2241 .enable_mask = BIT(0),
2254 .halt_reg = 0x0d88,
2256 .enable_reg = 0x0d88,
2257 .enable_mask = BIT(0),
2271 .halt_reg = 0x04ac,
2273 .enable_reg = 0x04ac,
2274 .enable_mask = BIT(0),
2287 .halt_reg = 0x04b4,
2289 .enable_reg = 0x04b4,
2290 .enable_mask = BIT(0),
2303 .halt_reg = 0x03c8,
2305 .enable_reg = 0x03c8,
2306 .enable_mask = BIT(0),
2320 .halt_reg = 0x03d0,
2322 .enable_reg = 0x03d0,
2323 .enable_mask = BIT(0),
2337 .halt_reg = 0x03cc,
2339 .enable_reg = 0x03cc,
2340 .enable_mask = BIT(0),
2353 .halt_reg = 0x0488,
2355 .enable_reg = 0x0488,
2356 .enable_mask = BIT(0),
2369 .halt_reg = 0x0484,
2371 .enable_reg = 0x0484,
2372 .enable_mask = BIT(0),
2386 .halt_reg = 0x0408,
2388 .enable_reg = 0x0408,
2389 .enable_mask = BIT(0),
2402 .halt_reg = 0x0410,
2404 .enable_reg = 0x0410,
2405 .enable_mask = BIT(0),
2419 .halt_reg = 0x0414,
2421 .enable_reg = 0x0414,
2422 .enable_mask = BIT(0),
2436 .halt_reg = 0x0418,
2438 .enable_reg = 0x0418,
2439 .enable_mask = BIT(0),
2452 .halt_reg = 0x040c,
2454 .enable_reg = 0x040c,
2455 .enable_mask = BIT(0),
2469 .gdscr = 0x404,
2564 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2565 [GCC_USB_HS_BCR] = { 0x0480 },
2566 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2577 .max_register = 0x1a80,
2740 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2741 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2742 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2743 [GCC_IMEM_BCR] = { 0x0200 },
2744 [GCC_MMSS_BCR] = { 0x0240 },
2745 [GCC_QDSS_BCR] = { 0x0300 },
2746 [GCC_USB_30_BCR] = { 0x03c0 },
2747 [GCC_USB3_PHY_BCR] = { 0x03fc },
2748 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2749 [GCC_USB_HS_BCR] = { 0x0480 },
2750 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2751 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2752 [GCC_SDCC1_BCR] = { 0x04c0 },
2753 [GCC_SDCC2_BCR] = { 0x0500 },
2754 [GCC_SDCC3_BCR] = { 0x0540 },
2755 [GCC_SDCC4_BCR] = { 0x0580 },
2756 [GCC_BLSP1_BCR] = { 0x05c0 },
2757 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2758 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2759 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2760 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2761 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2762 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2763 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2764 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2765 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2766 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2767 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2768 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2769 [GCC_BLSP2_BCR] = { 0x0940 },
2770 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2771 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2772 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2773 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2774 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2775 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2776 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2777 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2778 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2779 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2780 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2781 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2782 [GCC_PDM_BCR] = { 0x0cc0 },
2783 [GCC_BAM_DMA_BCR] = { 0x0d40 },
2784 [GCC_TSIF_BCR] = { 0x0d80 },
2785 [GCC_TCSR_BCR] = { 0x0dc0 },
2786 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2787 [GCC_MSG_RAM_BCR] = { 0x0e40 },
2788 [GCC_TLMM_BCR] = { 0x0e80 },
2789 [GCC_MPM_BCR] = { 0x0ec0 },
2790 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2791 [GCC_SPMI_BCR] = { 0x0fc0 },
2792 [GCC_SPDM_BCR] = { 0x1000 },
2793 [GCC_CE1_BCR] = { 0x1040 },
2794 [GCC_CE2_BCR] = { 0x1080 },
2795 [GCC_BIMC_BCR] = { 0x1100 },
2796 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2797 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2798 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2799 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2800 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2801 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2802 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2803 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2804 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2805 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2806 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2807 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2808 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2809 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2810 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2811 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2812 [GCC_DEHR_BCR] = { 0x1300 },
2813 [GCC_RBCPR_BCR] = { 0x1380 },
2814 [GCC_MSS_RESTART] = { 0x1680 },
2815 [GCC_LPASS_RESTART] = { 0x16c0 },
2816 [GCC_WCSS_RESTART] = { 0x1700 },
2817 [GCC_VENUS_RESTART] = { 0x1740 },
2828 .max_register = 0x1fc0,