Lines Matching +full:xo +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
17 #include "clk-regmap.h"
18 #include "clk-pll.h"
19 #include "clk-rcg.h"
20 #include "clk-branch.h"
21 #include "clk-alpha-pll.h"
22 #include "clk-regmap-divider.h"
23 #include "clk-regmap-mux.h"
60 .fw_name = "xo",
61 .name = "xo",
63 .num_parents = 1,
70 .mult = 1,
76 .num_parents = 1,
89 .num_parents = 1,
103 .fw_name = "xo",
104 .name = "xo",
106 .num_parents = 1,
121 .num_parents = 1,
135 .fw_name = "xo",
136 .name = "xo",
138 .num_parents = 1,
153 .num_parents = 1,
168 .fw_name = "xo",
169 .name = "xo",
171 .num_parents = 1,
186 .num_parents = 1,
192 .mult = 1,
198 .num_parents = 1,
213 .fw_name = "xo",
214 .name = "xo",
216 .num_parents = 1,
230 .num_parents = 1,
245 .fw_name = "xo",
246 .name = "xo",
248 .num_parents = 1,
262 .num_parents = 1,
268 F(19200000, P_XO, 1, 0, 0),
275 { .fw_name = "xo", .name = "xo" },
282 { P_GPLL0, 1 },
301 .mult = 1,
302 .div = 1,
307 .num_parents = 1,
317 .enable_mask = BIT(1),
324 .num_parents = 1,
332 F(19200000, P_XO, 1, 0, 0),
352 F(960000, P_XO, 10, 1, 2),
355 F(12500000, P_GPLL0_DIV2, 16, 1, 2),
356 F(16000000, P_GPLL0, 10, 1, 5),
357 F(19200000, P_XO, 1, 0, 0),
358 F(25000000, P_GPLL0, 16, 1, 2),
513 F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
514 F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
515 F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
516 F(16000000, P_GPLL0_DIV2, 5, 1, 5),
517 F(19200000, P_XO, 1, 0, 0),
518 F(24000000, P_GPLL0, 1, 3, 100),
519 F(25000000, P_GPLL0, 16, 1, 2),
520 F(32000000, P_GPLL0, 1, 1, 25),
521 F(40000000, P_GPLL0, 1, 1, 20),
522 F(46400000, P_GPLL0, 1, 29, 500),
523 F(48000000, P_GPLL0, 1, 3, 50),
524 F(51200000, P_GPLL0, 1, 8, 125),
525 F(56000000, P_GPLL0, 1, 7, 100),
526 F(58982400, P_GPLL0, 1, 1152, 15625),
527 F(60000000, P_GPLL0, 1, 3, 40),
528 F(64000000, P_GPLL0, 12.5, 1, 1),
617 { .fw_name = "xo" },
623 { P_GPLL0, 1 },
627 F(19200000, P_XO, 1, 0, 0),
646 F(19200000, P_XO, 1, 0, 0),
651 { .fw_name = "xo", .name = "xo" },
678 { .fw_name = "xo", .name = "xo" },
731 { .fw_name = "xo", .name = "xo" },
757 F(400000, P_XO, 12, 1, 4),
758 F(24000000, P_GPLL2, 12, 1, 4),
759 F(48000000, P_GPLL2, 12, 1, 2),
768 { .fw_name = "xo", .name = "xo" },
776 { P_GPLL0, 1 },
796 F(19200000, P_XO, 1, 0, 0),
803 { .fw_name = "xo", .name = "xo" },
811 { P_GPLL0, 1 },
852 { .fw_name = "xo", .name = "xo" },
860 { P_GPLL0, 1 },
878 F(19200000, P_XO, 1, 0, 0),
897 F(19200000, P_XO, 1, 0, 0),
898 F(20000000, P_GPLL6, 6, 1, 9),
899 F(60000000, P_GPLL6, 6, 1, 3),
904 { .fw_name = "xo", .name = "xo" },
912 { P_GPLL6, 1 },
933 { .fw_name = "xo", .name = "xo" },
1001 { .fw_name = "xo", .name = "xo" },
1029 .enable_mask = BIT(1),
1033 .fw_name = "xo",
1034 .name = "xo",
1036 .num_parents = 1,
1044 .mult = 1,
1050 .num_parents = 1,
1057 F(19200000, P_XO, 1, 0, 0),
1068 { .fw_name = "xo", .name = "xo" },
1076 { P_GPLL0, 1 },
1096 .mult = 1,
1097 .div = 1,
1102 .num_parents = 1,
1109 F(19200000, P_XO, 1, 0, 0),
1128 F(19200000, P_XO, 1, 0, 0),
1129 F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1134 { .fw_name = "xo", .name = "xo" },
1142 { P_BIAS_PLL_NSS_NOC, 1 },
1161 .mult = 1,
1162 .div = 1,
1167 .num_parents = 1,
1174 F(19200000, P_XO, 1, 0, 0),
1175 F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1180 { .fw_name = "xo", .name = "xo" },
1187 { P_NSS_CRYPTO_PLL, 1 },
1206 F(19200000, P_XO, 1, 0, 0),
1209 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1210 F(1689600000, P_UBI32_PLL, 1, 0, 0),
1215 { .fw_name = "xo", .name = "xo" },
1225 { P_UBI32_PLL, 1 },
1255 .num_parents = 1,
1285 .num_parents = 1,
1293 F(19200000, P_XO, 1, 0, 0),
1299 { .fw_name = "xo", .name = "xo" },
1305 { P_GPLL0_DIV2, 1 },
1322 F(19200000, P_XO, 1, 0, 0),
1328 { .fw_name = "xo", .name = "xo" },
1335 { P_GPLL0, 1 },
1353 F(19200000, P_XO, 1, 0, 0),
1354 F(300000000, P_BIAS_PLL, 1, 0, 0),
1359 { .fw_name = "xo", .name = "xo" },
1369 { P_BIAS_PLL, 1 },
1390 .mult = 1,
1396 .num_parents = 1,
1403 F(19200000, P_XO, 1, 0, 0),
1405 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1410 { .fw_name = "xo", .name = "xo" },
1419 { P_UNIPHY0_RX, 1 },
1447 .num_parents = 1,
1455 F(19200000, P_XO, 1, 0, 0),
1457 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1462 { .fw_name = "xo", .name = "xo" },
1471 { P_UNIPHY0_TX, 1 },
1499 .num_parents = 1,
1528 .num_parents = 1,
1557 .num_parents = 1,
1586 .num_parents = 1,
1615 .num_parents = 1,
1644 .num_parents = 1,
1673 .num_parents = 1,
1687 C(P_UNIPHY0_RX, 1, 0, 0),
1691 FMS(19200000, P_XO, 1, 0, 0),
1696 FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
1701 { .fw_name = "xo", .name = "xo" },
1713 { P_UNIPHY0_RX, 1 },
1743 .num_parents = 1,
1757 C(P_UNIPHY0_TX, 1, 0, 0),
1761 FMS(19200000, P_XO, 1, 0, 0),
1766 FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
1771 { .fw_name = "xo", .name = "xo" },
1783 { P_UNIPHY0_TX, 1 },
1813 .num_parents = 1,
1826 C(P_UNIPHY2_RX, 1, 0, 0),
1831 FMS(19200000, P_XO, 1, 0, 0),
1836 FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
1841 { .fw_name = "xo", .name = "xo" },
1850 { P_UNIPHY2_RX, 1 },
1878 .num_parents = 1,
1891 C(P_UNIPHY2_TX, 1, 0, 0),
1896 FMS(19200000, P_XO, 1, 0, 0),
1901 FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
1906 { .fw_name = "xo", .name = "xo" },
1915 { P_UNIPHY2_TX, 1 },
1943 .num_parents = 1,
1972 F(19200000, P_XO, 1, 0, 0),
1977 { .fw_name = "xo", .name = "xo" },
1986 { P_GPLL0, 1 },
2043 .num_parents = 1,
2059 .num_parents = 1,
2075 .num_parents = 1,
2091 .num_parents = 1,
2107 .num_parents = 1,
2123 .num_parents = 1,
2139 .num_parents = 1,
2155 .num_parents = 1,
2171 .num_parents = 1,
2187 .num_parents = 1,
2203 .num_parents = 1,
2219 .num_parents = 1,
2235 .num_parents = 1,
2251 .num_parents = 1,
2267 .num_parents = 1,
2283 .num_parents = 1,
2299 .num_parents = 1,
2315 .num_parents = 1,
2331 .num_parents = 1,
2348 .num_parents = 1,
2364 .num_parents = 1,
2380 .num_parents = 1,
2396 .num_parents = 1,
2412 .num_parents = 1,
2428 .num_parents = 1,
2444 .num_parents = 1,
2461 .num_parents = 1,
2477 .num_parents = 1,
2493 .num_parents = 1,
2509 .num_parents = 1,
2525 .num_parents = 1,
2541 .num_parents = 1,
2558 .num_parents = 1,
2574 .num_parents = 1,
2590 .num_parents = 1,
2606 .num_parents = 1,
2622 .num_parents = 1,
2638 .num_parents = 1,
2654 .num_parents = 1,
2671 .num_parents = 1,
2687 .num_parents = 1,
2703 .num_parents = 1,
2719 .num_parents = 1,
2735 .num_parents = 1,
2751 .num_parents = 1,
2767 .num_parents = 1,
2784 .num_parents = 1,
2800 .num_parents = 1,
2816 .num_parents = 1,
2832 .num_parents = 1,
2848 .num_parents = 1,
2864 .num_parents = 1,
2880 .num_parents = 1,
2896 .num_parents = 1,
2912 .num_parents = 1,
2928 .num_parents = 1,
2944 .num_parents = 1,
2960 .num_parents = 1,
2976 .num_parents = 1,
2992 .num_parents = 1,
3008 .num_parents = 1,
3024 .num_parents = 1,
3040 .num_parents = 1,
3056 .num_parents = 1,
3072 .num_parents = 1,
3088 .num_parents = 1,
3104 .num_parents = 1,
3120 .num_parents = 1,
3137 .num_parents = 1,
3153 .num_parents = 1,
3169 .num_parents = 1,
3185 .num_parents = 1,
3201 .num_parents = 1,
3217 .num_parents = 1,
3233 .num_parents = 1,
3249 .num_parents = 1,
3265 .num_parents = 1,
3281 .num_parents = 1,
3297 .num_parents = 1,
3314 .num_parents = 1,
3331 .num_parents = 1,
3348 .num_parents = 1,
3365 .num_parents = 1,
3382 .num_parents = 1,
3399 .num_parents = 1,
3416 .num_parents = 1,
3433 .num_parents = 1,
3450 .num_parents = 1,
3467 .num_parents = 1,
3483 .num_parents = 1,
3499 .num_parents = 1,
3515 .num_parents = 1,
3531 .num_parents = 1,
3547 .num_parents = 1,
3563 .num_parents = 1,
3579 .num_parents = 1,
3595 .num_parents = 1,
3611 .num_parents = 1,
3627 .num_parents = 1,
3643 .num_parents = 1,
3659 .num_parents = 1,
3675 .num_parents = 1,
3691 .num_parents = 1,
3707 .num_parents = 1,
3723 .num_parents = 1,
3739 .num_parents = 1,
3755 .num_parents = 1,
3771 .num_parents = 1,
3787 .num_parents = 1,
3803 .num_parents = 1,
3819 .num_parents = 1,
3835 .num_parents = 1,
3851 .num_parents = 1,
3867 .num_parents = 1,
3883 .num_parents = 1,
3899 .num_parents = 1,
3915 .num_parents = 1,
3931 .num_parents = 1,
3947 .num_parents = 1,
3963 .num_parents = 1,
3979 .num_parents = 1,
3995 .num_parents = 1,
4011 .num_parents = 1,
4027 .num_parents = 1,
4043 .num_parents = 1,
4059 .num_parents = 1,
4075 .num_parents = 1,
4091 .num_parents = 1,
4107 .num_parents = 1,
4123 .num_parents = 1,
4140 .num_parents = 1,
4152 .enable_mask = BIT(1),
4157 .num_parents = 1,
4174 .num_parents = 1,
4190 .num_parents = 1,
4206 .num_parents = 1,
4222 .num_parents = 1,
4230 F(19200000, P_XO, 1, 0, 0),
4253 .enable_mask = BIT(1),
4259 .num_parents = 1,
4277 .num_parents = 1,
4305 .aux_output_mask = BIT(1),
4659 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4687 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4695 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4702 [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
4704 [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
4706 [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
4709 [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
4723 { .compatible = "qcom,gcc-ipq8074" },
4763 return qcom_cc_really_probe(&pdev->dev, &gcc_ipq8074_desc, regmap); in gcc_ipq8074_probe()
4769 .name = "qcom,gcc-ipq8074",
4788 MODULE_ALIAS("platform:gcc-ipq8074");