Lines Matching +full:xo +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
18 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
21 #include "clk-regmap.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
25 #include "clk-regmap-divider.h"
45 * struct clk_fepll_vco - vco feedback divider corresponds for FEPLL clocks
61 * struct clk_fepll - clk divider corresponds to FEPLL clocks
90 const struct clk_fepll_vco *pll_vco = pll_div->pll_vco; in clk_fepll_vco_calc_rate()
94 regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv); in clk_fepll_vco_calc_rate()
95 refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) & in clk_fepll_vco_calc_rate()
96 (BIT(pll_vco->refclkdiv_width) - 1); in clk_fepll_vco_calc_rate()
97 fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) & in clk_fepll_vco_calc_rate()
98 (BIT(pll_vco->fdbkdiv_width) - 1); in clk_fepll_vco_calc_rate()
135 f = qcom_find_freq(pll->freq_tbl, rate); in clk_cpu_div_round_rate()
137 return -EINVAL; in clk_cpu_div_round_rate()
139 p_hw = clk_hw_get_parent_by_index(hw, f->src); in clk_cpu_div_round_rate()
142 return f->freq; in clk_cpu_div_round_rate()
157 f = qcom_find_freq(pll->freq_tbl, rate); in clk_cpu_div_set_rate()
159 return -EINVAL; in clk_cpu_div_set_rate()
161 mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; in clk_cpu_div_set_rate()
162 regmap_update_bits(pll->cdiv.clkr.regmap, in clk_cpu_div_set_rate()
163 pll->cdiv.reg, mask, in clk_cpu_div_set_rate()
164 f->pre_div << pll->cdiv.shift); in clk_cpu_div_set_rate()
169 udelay(1); in clk_cpu_div_set_rate()
188 regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); in clk_cpu_div_recalc_rate()
189 cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); in clk_cpu_div_recalc_rate()
197 pre_div = (cdiv + 1) * 2; in clk_cpu_div_recalc_rate()
241 .fw_name = "xo",
242 .name = "xo",
244 .num_parents = 1,
262 u32 cdiv, pre_div = 1; in clk_regmap_clk_div_recalc_rate()
266 if (pll->fixed_div) { in clk_regmap_clk_div_recalc_rate()
267 pre_div = pll->fixed_div; in clk_regmap_clk_div_recalc_rate()
269 regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); in clk_regmap_clk_div_recalc_rate()
270 cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); in clk_regmap_clk_div_recalc_rate()
272 for (clkt = pll->div_table; clkt->div; clkt++) { in clk_regmap_clk_div_recalc_rate()
273 if (clkt->val == cdiv) in clk_regmap_clk_div_recalc_rate()
274 pre_div = clkt->div; in clk_regmap_clk_div_recalc_rate()
294 .fw_name = "xo",
295 .name = "xo",
297 .num_parents = 1,
310 .fw_name = "xo",
311 .name = "xo",
313 .num_parents = 1,
326 .fw_name = "xo",
327 .name = "xo",
329 .num_parents = 1,
342 .fw_name = "xo",
343 .name = "xo",
345 .num_parents = 1,
358 .fw_name = "xo",
359 .name = "xo",
361 .num_parents = 1,
370 { 1, 16 },
384 .fw_name = "xo",
385 .name = "xo",
387 .num_parents = 1,
403 .fw_name = "xo",
404 .name = "xo",
406 .num_parents = 1,
416 { P_FEPLL200, 1 },
421 { .fw_name = "xo", .name = "xo" },
427 F(48000000, P_XO, 1, 0, 0),
454 .num_parents = 1,
464 { P_FEPLL200, 1 },
468 { .fw_name = "xo", .name = "xo" },
473 F(48000000, P_XO, 1, 0, 0),
474 F(200000000, P_FEPLL200, 1, 0, 0),
502 .num_parents = 1,
518 .num_parents = 1,
525 F(19050000, P_FEPLL200, 10.5, 1, 1),
551 .num_parents = 1,
580 .num_parents = 1,
593 { .fw_name = "xo", .name = "xo" },
598 F(960000, P_XO, 12, 1, 4),
599 F(4800000, P_XO, 1, 1, 10),
600 F(9600000, P_XO, 1, 1, 5),
601 F(15000000, P_XO, 1, 1, 3),
602 F(19200000, P_XO, 1, 2, 5),
603 F(24000000, P_XO, 1, 1, 2),
604 F(48000000, P_XO, 1, 0, 0),
631 .num_parents = 1,
661 .num_parents = 1,
669 F(1843200, P_FEPLL200, 1, 144, 15625),
670 F(3686400, P_FEPLL200, 1, 288, 15625),
671 F(7372800, P_FEPLL200, 1, 576, 15625),
672 F(14745600, P_FEPLL200, 1, 1152, 15625),
673 F(16000000, P_FEPLL200, 1, 2, 25),
674 F(24000000, P_XO, 1, 1, 2),
675 F(32000000, P_FEPLL200, 1, 4, 25),
676 F(40000000, P_FEPLL200, 1, 1, 5),
677 F(46400000, P_FEPLL200, 1, 29, 125),
678 F(48000000, P_XO, 1, 0, 0),
706 .num_parents = 1,
735 .num_parents = 1,
743 F(1250000, P_FEPLL200, 1, 16, 0),
744 F(2500000, P_FEPLL200, 1, 8, 0),
745 F(5000000, P_FEPLL200, 1, 4, 0),
772 .num_parents = 1,
802 .num_parents = 1,
832 .num_parents = 1,
841 { P_DDRPLL, 1 },
846 { .fw_name = "xo", .name = "xo" },
852 F(144000, P_XO, 1, 3, 240),
853 F(400000, P_XO, 1, 1, 0),
854 F(20000000, P_FEPLL500, 1, 1, 25),
855 F(25000000, P_FEPLL500, 1, 1, 20),
856 F(50000000, P_FEPLL500, 1, 1, 10),
857 F(100000000, P_FEPLL500, 1, 1, 5),
858 F(192000000, P_DDRPLL, 1, 0, 0),
877 F(48000000, P_XO, 1, 0, 0),
878 F(200000000, P_FEPLL200, 1, 0, 0),
879 F(384000000, P_DDRPLLAPSS, 1, 0, 0),
880 F(413000000, P_DDRPLLAPSS, 1, 0, 0),
881 F(448000000, P_DDRPLLAPSS, 1, 0, 0),
882 F(488000000, P_DDRPLLAPSS, 1, 0, 0),
883 F(500000000, P_FEPLL500, 1, 0, 0),
884 F(512000000, P_DDRPLLAPSS, 1, 0, 0),
885 F(537000000, P_DDRPLLAPSS, 1, 0, 0),
886 F(565000000, P_DDRPLLAPSS, 1, 0, 0),
887 F(597000000, P_DDRPLLAPSS, 1, 0, 0),
888 F(632000000, P_DDRPLLAPSS, 1, 0, 0),
889 F(672000000, P_DDRPLLAPSS, 1, 0, 0),
890 F(716000000, P_DDRPLLAPSS, 1, 0, 0),
898 { P_DDRPLLAPSS, 1 },
902 { .fw_name = "xo", .name = "xo" },
923 F(48000000, P_XO, 1, 0, 0),
951 .num_parents = 1,
968 .num_parents = 1,
982 .fw_name = "xo",
983 .name = "xo",
985 .num_parents = 1,
1000 .num_parents = 1,
1017 .num_parents = 1,
1028 .enable_mask = BIT(1),
1033 .num_parents = 1,
1049 .num_parents = 1,
1057 { P_FEPLL125DLY, 1 },
1061 { .fw_name = "xo", .name = "xo" },
1066 F(125000000, P_FEPLL125DLY, 1, 0, 0),
1092 .num_parents = 1,
1109 .num_parents = 1,
1124 .num_parents = 1,
1139 .num_parents = 1,
1154 .num_parents = 1,
1169 .num_parents = 1,
1185 .num_parents = 1,
1200 .num_parents = 1,
1215 .num_parents = 1,
1230 .num_parents = 1,
1245 .num_parents = 1,
1262 .num_parents = 1,
1277 .num_parents = 1,
1294 .num_parents = 1,
1327 .num_parents = 1,
1343 .num_parents = 1,
1360 .num_parents = 1,
1375 .num_parents = 1,
1384 { P_FEPLLWCSS2G, 1 },
1388 { .fw_name = "xo", .name = "xo" },
1393 F(48000000, P_XO, 1, 0, 0),
1394 F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
1421 .num_parents = 1,
1436 .fw_name = "xo",
1437 .name = "xo",
1439 .num_parents = 1,
1457 .num_parents = 1,
1465 { P_FEPLLWCSS5G, 1 },
1469 { .fw_name = "xo", .name = "xo" },
1474 F(48000000, P_XO, 1, 0, 0),
1475 F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
1501 .num_parents = 1,
1516 .fw_name = "xo",
1517 .name = "xo",
1519 .num_parents = 1,
1537 .num_parents = 1,
1621 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
1627 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
1644 [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
1689 [ESS_MAC2_ARES] = {0x1200C, 1},
1713 { .compatible = "qcom,gcc-ipq4019" },
1743 return devm_clk_notifier_register(&pdev->dev, apps_clk_src.clkr.hw.clk, in gcc_ipq4019_probe()
1750 .name = "qcom,gcc-ipq4019",
1767 MODULE_ALIAS("platform:gcc-ipq4019");