Lines Matching +full:0 +full:x8014
46 { 249600000, 2020000000, 0 },
51 .l = 0x24,
52 .alpha = 0x7555,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00182261,
55 .config_ctl_hi1_val = 0x32aa299c,
56 .user_ctl_val = 0x00000000,
57 .user_ctl_hi_val = 0x00000805,
61 .offset = 0x0,
66 .enable_reg = 0x0,
67 .enable_mask = BIT(0),
81 .l = 0x29,
82 .alpha = 0xfaaa,
83 .config_ctl_val = 0x20485699,
84 .config_ctl_hi_val = 0x00182261,
85 .config_ctl_hi1_val = 0x32aa299c,
86 .user_ctl_val = 0x00000000,
87 .user_ctl_hi_val = 0x00000805,
91 .offset = 0x1000,
96 .enable_reg = 0x0,
110 { P_BI_TCXO, 0 },
130 { P_BI_TCXO, 0 },
150 { P_BI_TCXO, 0 },
168 F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),
173 .cmd_rcgr = 0x9034,
174 .mnd_width = 0,
187 F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),
188 F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),
193 .cmd_rcgr = 0x9080,
194 .mnd_width = 0,
207 F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),
208 F(600000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1, 0, 0),
213 .cmd_rcgr = 0x904c,
214 .mnd_width = 0,
227 F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),
232 .cmd_rcgr = 0x9064,
233 .mnd_width = 0,
246 F(201500000, P_ECPRI_CC_PLL1_OUT_MAIN, 4, 0, 0),
247 F(403000000, P_ECPRI_CC_PLL1_OUT_MAIN, 2, 0, 0),
248 F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),
253 .cmd_rcgr = 0x81b0,
254 .mnd_width = 0,
267 F(100000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 6, 0, 0),
268 F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0),
273 .cmd_rcgr = 0x8150,
274 .mnd_width = 0,
287 .cmd_rcgr = 0x81c8,
288 .mnd_width = 0,
301 .cmd_rcgr = 0x8168,
302 .mnd_width = 0,
315 .cmd_rcgr = 0x8108,
316 .mnd_width = 0,
329 .cmd_rcgr = 0x8180,
330 .mnd_width = 0,
343 F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0),
348 .cmd_rcgr = 0x8120,
349 .mnd_width = 0,
362 .cmd_rcgr = 0x8198,
363 .mnd_width = 0,
376 .cmd_rcgr = 0x8138,
377 .mnd_width = 0,
390 F(533000000, P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 1, 0, 0),
391 F(700000000, P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 1, 0, 0),
392 F(806000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 1, 0, 0),
397 .cmd_rcgr = 0x8228,
398 .mnd_width = 0,
411 .cmd_rcgr = 0x8240,
412 .mnd_width = 0,
425 .cmd_rcgr = 0x81e0,
426 .mnd_width = 0,
439 .cmd_rcgr = 0x81f8,
440 .mnd_width = 0,
453 .cmd_rcgr = 0x8210,
454 .mnd_width = 0,
467 F(403000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 2, 0, 0),
472 .cmd_rcgr = 0xe00c,
473 .mnd_width = 0,
486 .reg = 0x907c,
487 .shift = 0,
501 .reg = 0x8290,
502 .shift = 0,
516 .reg = 0x8294,
517 .shift = 0,
531 .reg = 0x8298,
532 .shift = 0,
546 .reg = 0x829c,
547 .shift = 0,
561 .reg = 0x8260,
562 .shift = 0,
576 .reg = 0x8264,
577 .shift = 0,
591 .reg = 0x8268,
592 .shift = 0,
606 .reg = 0x826c,
607 .shift = 0,
621 .reg = 0x8270,
622 .shift = 0,
636 .reg = 0x8274,
637 .shift = 0,
651 .reg = 0x8278,
652 .shift = 0,
666 .reg = 0x827c,
667 .shift = 0,
681 .reg = 0x8280,
682 .shift = 0,
696 .reg = 0x8284,
697 .shift = 0,
711 .reg = 0x8288,
712 .shift = 0,
726 .reg = 0x828c,
727 .shift = 0,
741 .halt_reg = 0x900c,
744 .enable_reg = 0x900c,
745 .enable_mask = BIT(0),
759 .halt_reg = 0x902c,
762 .enable_reg = 0x902c,
763 .enable_mask = BIT(0),
777 .halt_reg = 0xf004,
780 .enable_reg = 0xf004,
781 .enable_mask = BIT(0),
795 .halt_reg = 0x9014,
798 .enable_reg = 0x9014,
799 .enable_mask = BIT(0),
813 .halt_reg = 0x901c,
816 .enable_reg = 0x901c,
817 .enable_mask = BIT(0),
831 .halt_reg = 0xf008,
834 .enable_reg = 0xf008,
835 .enable_mask = BIT(0),
849 .halt_reg = 0x9004,
852 .enable_reg = 0x9004,
853 .enable_mask = BIT(0),
867 .halt_reg = 0x9024,
870 .enable_reg = 0x9024,
871 .enable_mask = BIT(0),
885 .halt_reg = 0x80cc,
888 .enable_reg = 0x80cc,
889 .enable_mask = BIT(0),
903 .halt_reg = 0x80d0,
906 .enable_reg = 0x80d0,
907 .enable_mask = BIT(0),
921 .mem_enable_reg = 0x8410,
922 .mem_ack_reg = 0x8424,
923 .mem_enable_ack_mask = BIT(0),
925 .halt_reg = 0x80b4,
928 .enable_reg = 0x80b4,
929 .enable_mask = BIT(0),
944 .mem_enable_reg = 0x8410,
945 .mem_ack_reg = 0x8424,
948 .halt_reg = 0x80bc,
951 .enable_reg = 0x80bc,
952 .enable_mask = BIT(0),
967 .mem_enable_reg = 0x8410,
968 .mem_ack_reg = 0x8424,
971 .halt_reg = 0x80ac,
974 .enable_reg = 0x80ac,
975 .enable_mask = BIT(0),
990 .mem_enable_reg = 0x8414,
991 .mem_ack_reg = 0x8428,
992 .mem_enable_ack_mask = BIT(0),
994 .halt_reg = 0x80d8,
997 .enable_reg = 0x80d8,
998 .enable_mask = BIT(0),
1013 .mem_enable_reg = 0x8414,
1014 .mem_ack_reg = 0x8428,
1017 .halt_reg = 0x80e0,
1020 .enable_reg = 0x80e0,
1021 .enable_mask = BIT(0),
1036 .halt_reg = 0x80f0,
1039 .enable_reg = 0x80f0,
1040 .enable_mask = BIT(0),
1054 .mem_enable_reg = 0x8404,
1055 .mem_ack_reg = 0x8418,
1056 .mem_enable_ack_mask = BIT(0),
1058 .halt_reg = 0x800c,
1061 .enable_reg = 0x800c,
1062 .enable_mask = BIT(0),
1077 .mem_enable_reg = 0x8404,
1078 .mem_ack_reg = 0x8418,
1081 .halt_reg = 0x8014,
1084 .enable_reg = 0x8014,
1085 .enable_mask = BIT(0),
1100 .mem_enable_reg = 0x8404,
1101 .mem_ack_reg = 0x8418,
1104 .halt_reg = 0x801c,
1107 .enable_reg = 0x801c,
1108 .enable_mask = BIT(0),
1123 .mem_enable_reg = 0x8404,
1124 .mem_ack_reg = 0x8418,
1127 .halt_reg = 0x8024,
1130 .enable_reg = 0x8024,
1131 .enable_mask = BIT(0),
1146 .halt_reg = 0x8034,
1149 .enable_reg = 0x8034,
1150 .enable_mask = BIT(0),
1164 .mem_enable_reg = 0x8408,
1165 .mem_ack_reg = 0x841c,
1166 .mem_enable_ack_mask = BIT(0),
1168 .halt_reg = 0x8044,
1171 .enable_reg = 0x8044,
1172 .enable_mask = BIT(0),
1187 .mem_enable_reg = 0x8408,
1188 .mem_ack_reg = 0x841c,
1191 .halt_reg = 0x804c,
1194 .enable_reg = 0x804c,
1195 .enable_mask = BIT(0),
1210 .mem_enable_reg = 0x8408,
1211 .mem_ack_reg = 0x841c,
1214 .halt_reg = 0x8054,
1217 .enable_reg = 0x8054,
1218 .enable_mask = BIT(0),
1233 .mem_enable_reg = 0x8408,
1234 .mem_ack_reg = 0x841c,
1237 .halt_reg = 0x805c,
1240 .enable_reg = 0x805c,
1241 .enable_mask = BIT(0),
1256 .halt_reg = 0x806c,
1259 .enable_reg = 0x806c,
1260 .enable_mask = BIT(0),
1274 .mem_enable_reg = 0x840c,
1275 .mem_ack_reg = 0x8420,
1276 .mem_enable_ack_mask = BIT(0),
1278 .halt_reg = 0x807c,
1281 .enable_reg = 0x807c,
1282 .enable_mask = BIT(0),
1297 .mem_enable_reg = 0x840c,
1298 .mem_ack_reg = 0x8420,
1301 .halt_reg = 0x8084,
1304 .enable_reg = 0x8084,
1305 .enable_mask = BIT(0),
1320 .mem_enable_reg = 0x840c,
1321 .mem_ack_reg = 0x8420,
1324 .halt_reg = 0x808c,
1327 .enable_reg = 0x808c,
1328 .enable_mask = BIT(0),
1343 .mem_enable_reg = 0x840c,
1344 .mem_ack_reg = 0x8420,
1347 .halt_reg = 0x8094,
1350 .enable_reg = 0x8094,
1351 .enable_mask = BIT(0),
1366 .halt_reg = 0x80a4,
1369 .enable_reg = 0x80a4,
1370 .enable_mask = BIT(0),
1384 .mem_enable_reg = 0x8404,
1385 .mem_ack_reg = 0x8418,
1388 .halt_reg = 0x8004,
1391 .enable_reg = 0x8004,
1392 .enable_mask = BIT(0),
1407 .mem_enable_reg = 0x8408,
1408 .mem_ack_reg = 0x841c,
1411 .halt_reg = 0x803c,
1414 .enable_reg = 0x803c,
1415 .enable_mask = BIT(0),
1430 .mem_enable_reg = 0x840c,
1431 .mem_ack_reg = 0x8420,
1434 .halt_reg = 0x8074,
1437 .enable_reg = 0x8074,
1438 .enable_mask = BIT(0),
1453 .mem_enable_reg = 0x8410,
1454 .mem_ack_reg = 0x8424,
1457 .halt_reg = 0x80c4,
1460 .enable_reg = 0x80c4,
1461 .enable_mask = BIT(0),
1476 .mem_enable_reg = 0x8414,
1477 .mem_ack_reg = 0x8428,
1480 .halt_reg = 0x80e8,
1483 .enable_reg = 0x80e8,
1484 .enable_mask = BIT(0),
1499 .mem_enable_reg = 0x8404,
1500 .mem_ack_reg = 0x8418,
1503 .halt_reg = 0x802c,
1506 .enable_reg = 0x802c,
1507 .enable_mask = BIT(0),
1522 .mem_enable_reg = 0x8408,
1523 .mem_ack_reg = 0x841c,
1526 .halt_reg = 0x8064,
1529 .enable_reg = 0x8064,
1530 .enable_mask = BIT(0),
1545 .mem_enable_reg = 0x840c,
1546 .mem_ack_reg = 0x8420,
1549 .halt_reg = 0x809c,
1552 .enable_reg = 0x809c,
1553 .enable_mask = BIT(0),
1568 .halt_reg = 0x80f4,
1571 .enable_reg = 0x80f4,
1572 .enable_mask = BIT(0),
1586 .halt_reg = 0x80fc,
1589 .enable_reg = 0x80fc,
1590 .enable_mask = BIT(0),
1604 .mem_enable_reg = 0x8404,
1605 .mem_ack_reg = 0x8418,
1608 .halt_reg = 0xd140,
1611 .enable_reg = 0xd140,
1612 .enable_mask = BIT(0),
1622 .mem_enable_reg = 0x8408,
1623 .mem_ack_reg = 0x841C,
1626 .halt_reg = 0xd148,
1629 .enable_reg = 0xd148,
1630 .enable_mask = BIT(0),
1640 .mem_enable_reg = 0x840c,
1641 .mem_ack_reg = 0x8420,
1644 .halt_reg = 0xd150,
1647 .enable_reg = 0xd150,
1648 .enable_mask = BIT(0),
1658 .mem_enable_reg = 0x8410,
1659 .mem_ack_reg = 0x8424,
1662 .halt_reg = 0xd158,
1665 .enable_reg = 0xd158,
1666 .enable_mask = BIT(0),
1676 .mem_enable_reg = 0x8414,
1677 .mem_ack_reg = 0x8428,
1680 .halt_reg = 0xd160,
1683 .enable_reg = 0xd160,
1684 .enable_mask = BIT(0),
1694 .halt_reg = 0xe008,
1697 .enable_reg = 0xe008,
1698 .enable_mask = BIT(0),
1712 .halt_reg = 0xe004,
1715 .enable_reg = 0xe004,
1716 .enable_mask = BIT(0),
1730 .halt_reg = 0xd000,
1733 .enable_reg = 0xd000,
1734 .enable_mask = BIT(0),
1743 .halt_reg = 0xd050,
1746 .enable_reg = 0xd050,
1747 .enable_mask = BIT(0),
1756 .halt_reg = 0xd004,
1759 .enable_reg = 0xd004,
1760 .enable_mask = BIT(0),
1769 .halt_reg = 0xd054,
1772 .enable_reg = 0xd054,
1773 .enable_mask = BIT(0),
1782 .halt_reg = 0xd008,
1785 .enable_reg = 0xd008,
1786 .enable_mask = BIT(0),
1795 .halt_reg = 0xd058,
1798 .enable_reg = 0xd058,
1799 .enable_mask = BIT(0),
1808 .halt_reg = 0xd00c,
1811 .enable_reg = 0xd00c,
1812 .enable_mask = BIT(0),
1821 .halt_reg = 0xd05c,
1824 .enable_reg = 0xd05c,
1825 .enable_mask = BIT(0),
1834 .halt_reg = 0xd010,
1837 .enable_reg = 0xd010,
1838 .enable_mask = BIT(0),
1847 .halt_reg = 0xd060,
1850 .enable_reg = 0xd060,
1851 .enable_mask = BIT(0),
1860 .halt_reg = 0xd014,
1863 .enable_reg = 0xd014,
1864 .enable_mask = BIT(0),
1873 .halt_reg = 0xd064,
1876 .enable_reg = 0xd064,
1877 .enable_mask = BIT(0),
1886 .halt_reg = 0xd018,
1889 .enable_reg = 0xd018,
1890 .enable_mask = BIT(0),
1899 .halt_reg = 0xd068,
1902 .enable_reg = 0xd068,
1903 .enable_mask = BIT(0),
1912 .halt_reg = 0xd01c,
1915 .enable_reg = 0xd01c,
1916 .enable_mask = BIT(0),
1925 .halt_reg = 0xd06c,
1928 .enable_reg = 0xd06c,
1929 .enable_mask = BIT(0),
1938 .halt_reg = 0xd020,
1941 .enable_reg = 0xd020,
1942 .enable_mask = BIT(0),
1951 .halt_reg = 0xd070,
1954 .enable_reg = 0xd070,
1955 .enable_mask = BIT(0),
1964 .halt_reg = 0xd024,
1967 .enable_reg = 0xd024,
1968 .enable_mask = BIT(0),
1977 .halt_reg = 0xd074,
1980 .enable_reg = 0xd074,
1981 .enable_mask = BIT(0),
1990 .halt_reg = 0xd028,
1993 .enable_reg = 0xd028,
1994 .enable_mask = BIT(0),
2003 .halt_reg = 0xd078,
2006 .enable_reg = 0xd078,
2007 .enable_mask = BIT(0),
2016 .halt_reg = 0xd02c,
2019 .enable_reg = 0xd02c,
2020 .enable_mask = BIT(0),
2029 .halt_reg = 0xd07c,
2032 .enable_reg = 0xd07c,
2033 .enable_mask = BIT(0),
2042 .halt_reg = 0xd030,
2045 .enable_reg = 0xd030,
2046 .enable_mask = BIT(0),
2055 .halt_reg = 0xd080,
2058 .enable_reg = 0xd080,
2059 .enable_mask = BIT(0),
2068 .halt_reg = 0xd034,
2071 .enable_reg = 0xd034,
2072 .enable_mask = BIT(0),
2081 .halt_reg = 0xd084,
2084 .enable_reg = 0xd084,
2085 .enable_mask = BIT(0),
2094 .halt_reg = 0xd038,
2097 .enable_reg = 0xd038,
2098 .enable_mask = BIT(0),
2107 .halt_reg = 0xd088,
2110 .enable_reg = 0xd088,
2111 .enable_mask = BIT(0),
2120 .halt_reg = 0xd03c,
2123 .enable_reg = 0xd03c,
2124 .enable_mask = BIT(0),
2133 .halt_reg = 0xd08c,
2136 .enable_reg = 0xd08c,
2137 .enable_mask = BIT(0),
2146 .halt_reg = 0xd040,
2149 .enable_reg = 0xd040,
2150 .enable_mask = BIT(0),
2159 .halt_reg = 0xd090,
2162 .enable_reg = 0xd090,
2163 .enable_mask = BIT(0),
2172 .halt_reg = 0xd044,
2175 .enable_reg = 0xd044,
2176 .enable_mask = BIT(0),
2185 .halt_reg = 0xd094,
2188 .enable_reg = 0xd094,
2189 .enable_mask = BIT(0),
2198 .halt_reg = 0xd048,
2201 .enable_reg = 0xd048,
2202 .enable_mask = BIT(0),
2211 .halt_reg = 0xd098,
2214 .enable_reg = 0xd098,
2215 .enable_mask = BIT(0),
2224 .halt_reg = 0xd04c,
2227 .enable_reg = 0xd04c,
2228 .enable_mask = BIT(0),
2237 .halt_reg = 0xd09c,
2240 .enable_reg = 0xd09c,
2241 .enable_mask = BIT(0),
2399 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR] = { 0x9000 },
2400 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR] = { 0x80a8 },
2401 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR] = { 0x8000 },
2402 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR] = { 0x8038 },
2403 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR] = { 0x8070 },
2404 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR] = { 0x8104 },
2405 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR] = { 0xe000 },
2406 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR] = { 0xf000 },
2413 .max_register = 0x31bf0,