Lines Matching +full:0 +full:x8014
52 #define DISP_CC_MISC_CMD 0xF000
75 { 249600000, 2000000000, 0 },
79 .l = 0xD,
80 .alpha = 0x6492,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x32AA299C,
84 .user_ctl_val = 0x00000000,
85 .user_ctl_hi_val = 0x00000805,
89 .offset = 0x0,
106 .l = 0x1F,
107 .alpha = 0x4000,
108 .config_ctl_val = 0x20485699,
109 .config_ctl_hi_val = 0x00182261,
110 .config_ctl_hi1_val = 0x32AA299C,
111 .user_ctl_val = 0x00000000,
112 .user_ctl_hi_val = 0x00000805,
116 .offset = 0x1000,
133 { P_BI_TCXO, 0 },
151 { P_BI_TCXO, 0 },
163 { P_BI_TCXO, 0 },
179 { P_BI_TCXO, 0 },
195 { P_BI_TCXO, 0 },
207 { P_BI_TCXO, 0 },
221 { P_BI_TCXO, 0 },
233 { P_SLEEP_CLK, 0 },
241 F(19200000, P_BI_TCXO, 1, 0, 0),
242 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
243 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
248 .cmd_rcgr = 0x8324,
249 .mnd_width = 0,
263 F(19200000, P_BI_TCXO, 1, 0, 0),
268 .cmd_rcgr = 0x8134,
269 .mnd_width = 0,
283 .cmd_rcgr = 0x8150,
284 .mnd_width = 0,
298 .cmd_rcgr = 0x81ec,
299 .mnd_width = 0,
313 .cmd_rcgr = 0x819c,
314 .mnd_width = 0,
327 .cmd_rcgr = 0x81bc,
342 .cmd_rcgr = 0x81d4,
357 .cmd_rcgr = 0x8254,
358 .mnd_width = 0,
372 .cmd_rcgr = 0x8234,
373 .mnd_width = 0,
386 .cmd_rcgr = 0x8204,
401 .cmd_rcgr = 0x821c,
416 .cmd_rcgr = 0x82bc,
417 .mnd_width = 0,
431 .cmd_rcgr = 0x826c,
432 .mnd_width = 0,
445 .cmd_rcgr = 0x828c,
460 .cmd_rcgr = 0x82a4,
475 .cmd_rcgr = 0x8308,
476 .mnd_width = 0,
490 .cmd_rcgr = 0x82ec,
491 .mnd_width = 0,
504 .cmd_rcgr = 0x82d4,
519 .cmd_rcgr = 0x816c,
520 .mnd_width = 0,
534 .cmd_rcgr = 0x8184,
535 .mnd_width = 0,
549 F(19200000, P_BI_TCXO, 1, 0, 0),
550 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
551 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
552 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
553 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
554 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
555 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
556 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
557 F(500000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
562 .cmd_rcgr = 0x80ec,
563 .mnd_width = 0,
577 .cmd_rcgr = 0x80bc,
592 .cmd_rcgr = 0x80d4,
607 F(19200000, P_BI_TCXO, 1, 0, 0),
608 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
609 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
610 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
615 .cmd_rcgr = 0x8104,
616 .mnd_width = 0,
630 .cmd_rcgr = 0x811c,
631 .mnd_width = 0,
645 F(32000, P_SLEEP_CLK, 1, 0, 0),
650 .cmd_rcgr = 0xe060,
651 .mnd_width = 0,
665 .cmd_rcgr = 0xe044,
666 .mnd_width = 0,
680 .reg = 0x814c,
681 .shift = 0,
694 .reg = 0x8168,
695 .shift = 0,
708 .reg = 0x81b4,
709 .shift = 0,
723 .reg = 0x824c,
724 .shift = 0,
738 .reg = 0x8284,
739 .shift = 0,
753 .reg = 0x8304,
754 .shift = 0,
768 .halt_reg = 0xa020,
771 .enable_reg = 0xa020,
772 .enable_mask = BIT(0),
786 .halt_reg = 0x80a4,
789 .enable_reg = 0x80a4,
790 .enable_mask = BIT(0),
804 .halt_reg = 0x8028,
807 .enable_reg = 0x8028,
808 .enable_mask = BIT(0),
822 .halt_reg = 0x802c,
825 .enable_reg = 0x802c,
826 .enable_mask = BIT(0),
840 .halt_reg = 0x8030,
843 .enable_reg = 0x8030,
844 .enable_mask = BIT(0),
858 .halt_reg = 0x8034,
861 .enable_reg = 0x8034,
862 .enable_mask = BIT(0),
876 .halt_reg = 0x8058,
879 .enable_reg = 0x8058,
880 .enable_mask = BIT(0),
894 .halt_reg = 0x804c,
897 .enable_reg = 0x804c,
898 .enable_mask = BIT(0),
912 .halt_reg = 0x8040,
915 .enable_reg = 0x8040,
916 .enable_mask = BIT(0),
930 .halt_reg = 0x8048,
933 .enable_reg = 0x8048,
934 .enable_mask = BIT(0),
948 .halt_reg = 0x8050,
951 .enable_reg = 0x8050,
952 .enable_mask = BIT(0),
966 .halt_reg = 0x8054,
969 .enable_reg = 0x8054,
970 .enable_mask = BIT(0),
984 .halt_reg = 0x8044,
987 .enable_reg = 0x8044,
988 .enable_mask = BIT(0),
1002 .halt_reg = 0x8074,
1005 .enable_reg = 0x8074,
1006 .enable_mask = BIT(0),
1020 .halt_reg = 0x8070,
1023 .enable_reg = 0x8070,
1024 .enable_mask = BIT(0),
1038 .halt_reg = 0x8064,
1041 .enable_reg = 0x8064,
1042 .enable_mask = BIT(0),
1056 .halt_reg = 0x806c,
1059 .enable_reg = 0x806c,
1060 .enable_mask = BIT(0),
1074 .halt_reg = 0x805c,
1077 .enable_reg = 0x805c,
1078 .enable_mask = BIT(0),
1092 .halt_reg = 0x8060,
1095 .enable_reg = 0x8060,
1096 .enable_mask = BIT(0),
1110 .halt_reg = 0x8068,
1113 .enable_reg = 0x8068,
1114 .enable_mask = BIT(0),
1128 .halt_reg = 0x808c,
1131 .enable_reg = 0x808c,
1132 .enable_mask = BIT(0),
1146 .halt_reg = 0x8088,
1149 .enable_reg = 0x8088,
1150 .enable_mask = BIT(0),
1164 .halt_reg = 0x8080,
1167 .enable_reg = 0x8080,
1168 .enable_mask = BIT(0),
1182 .halt_reg = 0x8084,
1185 .enable_reg = 0x8084,
1186 .enable_mask = BIT(0),
1200 .halt_reg = 0x8078,
1203 .enable_reg = 0x8078,
1204 .enable_mask = BIT(0),
1218 .halt_reg = 0x807c,
1221 .enable_reg = 0x807c,
1222 .enable_mask = BIT(0),
1236 .halt_reg = 0x809c,
1239 .enable_reg = 0x809c,
1240 .enable_mask = BIT(0),
1254 .halt_reg = 0x80a0,
1257 .enable_reg = 0x80a0,
1258 .enable_mask = BIT(0),
1272 .halt_reg = 0x8094,
1275 .enable_reg = 0x8094,
1276 .enable_mask = BIT(0),
1290 .halt_reg = 0x8098,
1293 .enable_reg = 0x8098,
1294 .enable_mask = BIT(0),
1308 .halt_reg = 0x8090,
1311 .enable_reg = 0x8090,
1312 .enable_mask = BIT(0),
1326 .halt_reg = 0x8038,
1329 .enable_reg = 0x8038,
1330 .enable_mask = BIT(0),
1344 .halt_reg = 0x803c,
1347 .enable_reg = 0x803c,
1348 .enable_mask = BIT(0),
1362 .halt_reg = 0xa004,
1365 .enable_reg = 0xa004,
1366 .enable_mask = BIT(0),
1380 .halt_reg = 0x800c,
1383 .enable_reg = 0x800c,
1384 .enable_mask = BIT(0),
1398 .halt_reg = 0xa014,
1401 .enable_reg = 0xa014,
1402 .enable_mask = BIT(0),
1416 .halt_reg = 0x801c,
1419 .enable_reg = 0x801c,
1420 .enable_mask = BIT(0),
1434 .halt_reg = 0xc004,
1437 .enable_reg = 0xc004,
1438 .enable_mask = BIT(0),
1452 .halt_reg = 0x8004,
1455 .enable_reg = 0x8004,
1456 .enable_mask = BIT(0),
1470 .halt_reg = 0x8008,
1473 .enable_reg = 0x8008,
1474 .enable_mask = BIT(0),
1488 .halt_reg = 0xa00c,
1491 .enable_reg = 0xa00c,
1492 .enable_mask = BIT(0),
1506 .halt_reg = 0x8014,
1509 .enable_reg = 0x8014,
1510 .enable_mask = BIT(0),
1524 .halt_reg = 0xc00c,
1527 .enable_reg = 0xc00c,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0xc008,
1545 .enable_reg = 0xc008,
1546 .enable_mask = BIT(0),
1560 .halt_reg = 0xa01c,
1563 .enable_reg = 0xa01c,
1564 .enable_mask = BIT(0),
1578 .halt_reg = 0x8024,
1581 .enable_reg = 0x8024,
1582 .enable_mask = BIT(0),
1596 .halt_reg = 0xe078,
1599 .enable_reg = 0xe078,
1600 .enable_mask = BIT(0),
1614 .gdscr = 0x9000,
1623 .gdscr = 0xb000,
1719 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1720 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1721 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1733 .max_register = 0x11008,
1776 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); in disp_cc_sm8450_probe()
1779 qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ in disp_cc_sm8450_probe()
1787 return 0; in disp_cc_sm8450_probe()