clk/qcom/dispcc-sm4450.c

46 	{ 249600000, 2020000000, 0 },
51 	.l = 0x1f,
52 	.alpha = 0x4000,
53 	.config_ctl_val = 0x20485699,
54 	.config_ctl_hi_val = 0x00182261,
55 	.config_ctl_hi1_val = 0x32aa299c,
56 	.user_ctl_val = 0x00000000,
57 	.user_ctl_hi_val = 0x00000805,
61 	.offset = 0x0,
78 	.offset = 0x1000,
95 	{ P_BI_TCXO, 0 },
107 	{ P_BI_TCXO, 0 },
121 	{ P_BI_TCXO, 0 },
133 	{ P_BI_TCXO, 0 },
145 	{ P_BI_TCXO, 0 },
155 	{ P_SLEEP_CLK, 0 },
163 	F(19200000, P_BI_TCXO, 1, 0, 0),
164 	F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
165 	F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
170 	.cmd_rcgr = 0x82a4,
171 	.mnd_width = 0,
185 	F(19200000, P_BI_TCXO, 1, 0, 0),
190 	.cmd_rcgr = 0x80f8,
191 	.mnd_width = 0,
205 	.cmd_rcgr = 0x8114,
206 	.mnd_width = 0,
220 	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
221 	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
222 	F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
223 	F(506000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
224 	F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
229 	.cmd_rcgr = 0x80b0,
230 	.mnd_width = 0,
244 	.cmd_rcgr = 0x8098,
259 	F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
260 	F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
265 	.cmd_rcgr = 0x80c8,
266 	.mnd_width = 0,
280 	.cmd_rcgr = 0x80e0,
281 	.mnd_width = 0,
295 	F(32000, P_SLEEP_CLK, 1, 0, 0),
300 	.cmd_rcgr = 0xe058,
301 	.mnd_width = 0,
315 	.cmd_rcgr = 0xe03c,
316 	.mnd_width = 0,
330 	.reg = 0x8110,
331 	.shift = 0,
345 	.halt_reg = 0xa020,
348 		.enable_reg = 0xa020,
349 		.enable_mask = BIT(0),
363 	.halt_reg = 0x8094,
366 		.enable_reg = 0x8094,
367 		.enable_mask = BIT(0),
381 	.halt_reg = 0x8024,
384 		.enable_reg = 0x8024,
385 		.enable_mask = BIT(0),
399 	.halt_reg = 0x8028,
402 		.enable_reg = 0x8028,
403 		.enable_mask = BIT(0),
417 	.halt_reg = 0x802c,
420 		.enable_reg = 0x802c,
421 		.enable_mask = BIT(0),
435 	.halt_reg = 0xa004,
438 		.enable_reg = 0xa004,
439 		.enable_mask = BIT(0),
453 	.halt_reg = 0x8008,
456 		.enable_reg = 0x8008,
457 		.enable_mask = BIT(0),
471 	.halt_reg = 0xa014,
474 		.enable_reg = 0xa014,
475 		.enable_mask = BIT(0),
489 	.halt_reg = 0x8018,
492 		.enable_reg = 0x8018,
493 		.enable_mask = BIT(0),
507 	.halt_reg = 0xc004,
510 		.enable_reg = 0xc004,
511 		.enable_mask = BIT(0),
525 	.halt_reg = 0x8004,
528 		.enable_reg = 0x8004,
529 		.enable_mask = BIT(0),
543 	.halt_reg = 0xa00c,
546 		.enable_reg = 0xa00c,
547 		.enable_mask = BIT(0),
561 	.halt_reg = 0x8010,
564 		.enable_reg = 0x8010,
565 		.enable_mask = BIT(0),
579 	.halt_reg = 0xc00c,
582 		.enable_reg = 0xc00c,
583 		.enable_mask = BIT(0),
597 	.halt_reg = 0xc008,
600 		.enable_reg = 0xc008,
601 		.enable_mask = BIT(0),
615 	.halt_reg = 0xa01c,
618 		.enable_reg = 0xa01c,
619 		.enable_mask = BIT(0),
633 	.halt_reg = 0x8020,
636 		.enable_reg = 0x8020,
637 		.enable_mask = BIT(0),
651 	.gdscr = 0x9000,
652 	.en_rest_wait_val = 0x2,
653 	.en_few_wait_val = 0x2,
654 	.clk_dis_wait_val = 0xf,
663 	.gdscr = 0xb000,
664 	.en_rest_wait_val = 0x2,
665 	.en_few_wait_val = 0x2,
666 	.clk_dis_wait_val = 0xf,
712 	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
713 	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
714 	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
721 	.max_register = 0x11008,
753 	qcom_branch_set_clk_en(regmap, 0xe070); /* DISP_CC_SLEEP_CLK */  in disp_cc_sm4450_probe()
754 	qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */  in disp_cc_sm4450_probe()