clk/qcom/clk-cpu-8996.c

1 // SPDX-License-Identifier: GPL-2.0
7  * Each of the CPU clusters (Power and Perf) on msm8996 are
12  *                              +-------+
14  *           +------------------>0      |
16  *           +------------------>3      |
18  *                    PLL/2     | SMUX  +----+
19  *                      +------->1      |    |
21  *                      |       +-------+    |    +-------+
22  *                      |                    +---->0      |
24  * +---------------+    |             +----------->1      | CPU clk
25  * |Primary PLL    +----+ PLL_EARLY   |           |       +------>
26  * |               +------+-----------+    +------>2 PMUX |
27  * +---------------+      |                |      |       |
28  *                        |   +------+     |   +-->3      |
29  *                        +--^+  ACD +-----+   |  +-------+
30  * +---------------+          +------+         |
32  * |               +---------------------------+
33  * +---------------+         PLL_EARLY
46  *  Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
48  *  Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
56 #include <linux/clk-provider.h>
61 #include <soc/qcom/kryo-l2-accessors.h>
65 #include "clk-alpha-pll.h"
66 #include "clk-regmap.h"
67 #include "clk-regmap-mux.h"
280 	regmap_read(clkr->regmap, cpuclk->reg, &val);  in clk_cpu_8996_pmux_get_parent()
293 	return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val);  in clk_cpu_8996_pmux_set_parent()
301 	if (req->rate < (DIV_2_THRESHOLD / 2))  in clk_cpu_8996_pmux_determine_rate()
302 		return -EINVAL;  in clk_cpu_8996_pmux_determine_rate()
304 	if (req->rate < DIV_2_THRESHOLD)  in clk_cpu_8996_pmux_determine_rate()
309 		return -EINVAL;  in clk_cpu_8996_pmux_determine_rate()
311 	req->best_parent_rate = clk_hw_round_rate(parent, req->rate);  in clk_cpu_8996_pmux_determine_rate()
312 	req->best_parent_hw = parent;  in clk_cpu_8996_pmux_determine_rate()
450 	/* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */  in qcom_cpu_clk_msm8996_register_clks()
477 	/* Pulse swallower and soft-start settings */  in qcom_cpu_clk_msm8996_register_clks()
554 		qcom_cpu_clk_msm8996_acd_init(cpuclk->clkr.regmap);  in cpu_clk_notifier_cb()
564 		if (cnd->new_rate < DIV_2_THRESHOLD &&  in cpu_clk_notifier_cb()
565 		    cnd->old_rate > DIV_2_THRESHOLD)  in cpu_clk_notifier_cb()
566 			clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, SMUX_INDEX);  in cpu_clk_notifier_cb()
571 		if (cnd->new_rate < DIV_2_THRESHOLD &&  in cpu_clk_notifier_cb()
572 		    cnd->old_rate > DIV_2_THRESHOLD)  in cpu_clk_notifier_cb()
573 			clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ACD_INDEX);  in cpu_clk_notifier_cb()
587 	struct device *dev = &pdev->dev;  in qcom_cpu_clk_msm8996_driver_probe()
592 		return -ENOMEM;  in qcom_cpu_clk_msm8996_driver_probe()
593 	data->num = 2;  in qcom_cpu_clk_msm8996_driver_probe()
607 	data->hws[0] = &pwrcl_pmux.clkr.hw;  in qcom_cpu_clk_msm8996_driver_probe()
608 	data->hws[1] = &perfcl_pmux.clkr.hw;  in qcom_cpu_clk_msm8996_driver_probe()
614 	{ .compatible = "qcom,msm8996-apcc" },
622 		.name = "qcom-msm8996-apcc",
628 MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");