clk/qcom/clk-alpha-pll.h

1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
70 #define VCO(a, b, c) { \  macro
77  * struct clk_alpha_pll - phase locked loop (PLL)
78  * @offset: base address of registers
80  * @vco_table: array of VCO settings
81  * @num_vco: number of VCO settings in @vco_table
86 	u32 offset;  member
101  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
102  * @offset: base address of registers
104  * @width: width of post-divider
105  * @post_div_shift: shift to differentiate between odd & even post-divider
106  * @post_div_table: table with PLL odd and even post-divider settings
107  * @num_post_div: Number of PLL post-divider settings
112 	u32 offset;  member