Lines Matching full:pll
13 #include "clk-alpha-pll.h"
295 /* TRION PLL specific settings and offsets */
299 /* LUCID PLL specific settings and offsets */
302 /* LUCID 5LPE PLL specific settings and offsets */
308 /* LUCID EVO PLL specific settings and offsets */
315 /* ZONDA PLL specific */
332 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
338 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
340 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
345 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
360 #define wait_for_pll_enable_active(pll) \ argument
361 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
363 #define wait_for_pll_enable_lock(pll) \ argument
364 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
366 #define wait_for_zonda_pll_freq_lock(pll) \ argument
367 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
369 #define wait_for_pll_disable(pll) \ argument
370 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
372 #define wait_for_pll_offline(pll) \ argument
373 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
375 #define wait_for_pll_update(pll) \ argument
376 wait_for_pll(pll, PLL_UPDATE, 1, "update")
378 #define wait_for_pll_update_ack_set(pll) \ argument
379 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
381 #define wait_for_pll_update_ack_clear(pll) \ argument
382 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
391 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
396 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
397 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
398 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
400 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
401 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
404 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
405 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
425 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
428 regmap_update_bits(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
432 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
436 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
440 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
443 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
444 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
451 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
454 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
460 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
463 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
470 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
476 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
479 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
483 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
484 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
489 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
495 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
500 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
506 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
509 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
529 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
533 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
542 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
549 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
561 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
566 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
570 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
581 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
584 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
595 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
602 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
640 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
642 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
643 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
657 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
658 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
660 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
662 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
664 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
666 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
681 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
686 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
688 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
689 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
696 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
697 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
698 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
700 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
703 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
707 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
709 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
714 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
718 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
724 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
727 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
728 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
731 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
738 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
740 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
744 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
745 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
746 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
751 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
757 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
759 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
762 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
767 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
770 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
790 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_round_rate() local
791 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_round_rate()
796 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
799 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
800 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
805 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_huayra_2290_pll_configure() argument
810 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_huayra_2290_pll_configure()
811 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_huayra_2290_pll_configure()
812 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_huayra_2290_pll_configure()
813 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_huayra_2290_pll_configure()
814 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_huayra_2290_pll_configure()
815 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_huayra_2290_pll_configure()
816 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_huayra_2290_pll_configure()
817 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_huayra_2290_pll_configure()
818 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_huayra_2290_pll_configure()
821 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_huayra_2290_pll_configure()
822 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
827 /* Take PLL out from reset state */ in clk_huayra_2290_pll_configure()
828 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_huayra_2290_pll_configure()
829 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
834 /* Enable PLL output */ in clk_huayra_2290_pll_configure()
835 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_huayra_2290_pll_configure()
890 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
893 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
894 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
897 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
943 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
948 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
951 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
954 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
964 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
967 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
970 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
971 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
974 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
977 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
991 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
997 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
998 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
1007 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
1009 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
1014 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
1015 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
1019 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
1028 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
1032 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
1034 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
1038 /* Enable the PLL outputs */ in clk_trion_pll_enable()
1039 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
1044 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
1045 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
1051 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
1052 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
1056 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
1066 /* Disable the global PLL output */ in clk_trion_pll_disable()
1067 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
1071 /* Disable the PLL outputs */ in clk_trion_pll_disable()
1072 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
1077 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
1078 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
1079 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
1085 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
1086 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
1088 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
1089 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
1144 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
1147 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
1150 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
1175 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_rate() local
1178 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
1184 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
1191 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_round_ro_rate() local
1194 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
1197 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
1209 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1215 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1216 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1233 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1238 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1239 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1240 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1242 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1244 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1246 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1248 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1250 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1256 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1259 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) in clk_fabia_pll_configure()
1260 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, in clk_fabia_pll_configure()
1263 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1266 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1273 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1275 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1277 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1286 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1289 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1293 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1297 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1301 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1305 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1310 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1314 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1318 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1323 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1330 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1332 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1334 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1344 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1349 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1353 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1354 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1360 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1361 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1363 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1364 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1390 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1391 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1402 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1403 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1405 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1410 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1414 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1419 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1420 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1428 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1430 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1434 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1435 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1448 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1449 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1451 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1454 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1486 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1490 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1494 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1495 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1497 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1498 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1499 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1510 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1511 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1514 regmap_read(regmap, PLL_USER_CTL(pll), &val); in clk_trion_pll_postdiv_recalc_rate()
1516 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1517 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1519 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1520 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1521 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1533 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_round_rate() local
1535 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1536 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1543 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1544 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1548 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1549 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1550 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1555 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1556 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, in clk_trion_pll_postdiv_set_rate()
1557 val << pll->post_div_shift); in clk_trion_pll_postdiv_set_rate()
1570 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_round_rate() local
1572 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1573 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1579 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1583 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1586 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1594 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1595 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1596 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1601 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1602 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1603 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1614 * clk_trion_pll_configure - configure the trion pll
1616 * @pll: clk alpha pll
1618 * @config: configuration to apply for pll
1620 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1624 * If the bootloader left the PLL enabled it's likely that there are in clk_trion_pll_configure()
1625 * RCGs that will lock up if we disable the PLL below. in clk_trion_pll_configure()
1627 if (trion_pll_is_enabled(pll, regmap)) { in clk_trion_pll_configure()
1628 pr_debug("Trion PLL is already enabled, skipping configuration\n"); in clk_trion_pll_configure()
1632 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1633 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1634 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1635 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1637 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1639 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1641 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1643 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1645 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1647 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1649 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1651 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1654 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1657 /* Disable PLL output */ in clk_trion_pll_configure()
1658 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1661 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1663 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1664 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1669 * The TRION PLL requires a power-on self-calibration which happens when the
1670 * PLL comes out of reset. Calibrate in case it is not completed.
1674 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1679 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1704 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1706 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1716 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); in __alpha_pll_trion_set_rate()
1717 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1719 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1720 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1726 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1728 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1733 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1738 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1743 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1783 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1786 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1787 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1788 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1790 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1792 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1794 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1796 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1804 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1805 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1816 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1817 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1820 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1836 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1838 * @pll: clk alpha pll
1840 * @config: configuration to apply for pll
1842 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_5lpe_pll_configure() argument
1846 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_5lpe_pll_configure()
1847 * RCGs that will lock up if we disable the PLL below. in clk_lucid_5lpe_pll_configure()
1849 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_5lpe_pll_configure()
1850 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); in clk_lucid_5lpe_pll_configure()
1854 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_lucid_5lpe_pll_configure()
1855 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_lucid_5lpe_pll_configure()
1856 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_5lpe_pll_configure()
1857 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_lucid_5lpe_pll_configure()
1859 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1861 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1863 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_lucid_5lpe_pll_configure()
1865 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1867 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1869 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_lucid_5lpe_pll_configure()
1871 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1873 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1876 /* Disable PLL output */ in clk_lucid_5lpe_pll_configure()
1877 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_5lpe_pll_configure()
1880 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_5lpe_pll_configure()
1882 /* Place the PLL in STANDBY mode */ in clk_lucid_5lpe_pll_configure()
1883 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_5lpe_pll_configure()
1889 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1893 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1902 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1905 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1906 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); in alpha_pll_lucid_5lpe_enable()
1910 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
1914 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
1916 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1920 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1921 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
1925 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
1926 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
1931 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
1935 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
1945 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
1946 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
1950 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
1951 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
1955 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
1956 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
1960 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1961 * when the PLL comes out of reset. Calibrate in case it is not completed.
1965 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
1971 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
2000 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in __clk_lucid_pll_postdiv_set_rate() local
2001 struct regmap *regmap = pll->clkr.regmap; in __clk_lucid_pll_postdiv_set_rate()
2006 * If the PLL is in FSM mode, then treat set_rate callback as a in __clk_lucid_pll_postdiv_set_rate()
2009 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in __clk_lucid_pll_postdiv_set_rate()
2016 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
2017 pr_err("Missing the post_div_table for the %s PLL\n", in __clk_lucid_pll_postdiv_set_rate()
2018 clk_hw_get_name(&pll->clkr.hw)); in __clk_lucid_pll_postdiv_set_rate()
2023 for (i = 0; i < pll->num_post_div; i++) { in __clk_lucid_pll_postdiv_set_rate()
2024 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
2025 val = pll->post_div_table[i].val; in __clk_lucid_pll_postdiv_set_rate()
2030 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2031 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_lucid_pll_postdiv_set_rate()
2032 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2068 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
2071 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
2072 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
2073 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
2074 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
2075 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
2076 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
2077 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
2078 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
2079 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
2080 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
2081 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
2083 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
2085 /* Disable PLL output */ in clk_zonda_pll_configure()
2086 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
2089 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
2091 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
2092 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
2098 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
2099 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
2103 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
2110 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
2113 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
2114 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
2122 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
2125 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
2127 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
2131 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
2133 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
2137 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
2138 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
2140 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
2141 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
2148 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
2149 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
2152 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
2160 /* Disable the global PLL output */ in clk_zonda_pll_disable()
2161 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
2163 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
2164 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
2166 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
2167 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
2169 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
2170 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
2186 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
2189 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
2202 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
2203 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
2212 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
2216 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
2218 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
2222 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()
2237 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_evo_pll_configure() argument
2243 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_evo_pll_configure()
2244 * RCGs that will lock up if we disable the PLL below. in clk_lucid_evo_pll_configure()
2246 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_evo_pll_configure()
2247 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); in clk_lucid_evo_pll_configure()
2252 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_evo_pll_configure()
2253 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_evo_pll_configure()
2254 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_evo_pll_configure()
2255 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_evo_pll_configure()
2256 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2257 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_evo_pll_configure()
2258 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_evo_pll_configure()
2259 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_evo_pll_configure()
2260 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_evo_pll_configure()
2261 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2262 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_evo_pll_configure()
2264 /* Disable PLL output */ in clk_lucid_evo_pll_configure()
2265 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_evo_pll_configure()
2268 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_evo_pll_configure()
2269 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_evo_pll_configure()
2273 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_ole_pll_configure() argument
2280 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_ole_pll_configure()
2281 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_ole_pll_configure()
2282 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_ole_pll_configure()
2283 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_ole_pll_configure()
2284 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2285 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_ole_pll_configure()
2286 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_ole_pll_configure()
2287 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_ole_pll_configure()
2288 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_ole_pll_configure()
2289 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2290 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_ole_pll_configure()
2292 /* Disable PLL output */ in clk_lucid_ole_pll_configure()
2293 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_ole_pll_configure()
2296 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_ole_pll_configure()
2297 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_ole_pll_configure()
2303 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_enable() local
2304 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_enable()
2308 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_evo_enable()
2317 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2320 /* Check if PLL is already enabled */ in alpha_pll_lucid_evo_enable()
2321 ret = trion_pll_is_enabled(pll, regmap); in alpha_pll_lucid_evo_enable()
2325 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); in alpha_pll_lucid_evo_enable()
2329 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_evo_enable()
2334 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_evo_enable()
2336 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2340 /* Enable the PLL outputs */ in alpha_pll_lucid_evo_enable()
2341 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_evo_enable()
2345 /* Enable the global PLL outputs */ in alpha_pll_lucid_evo_enable()
2346 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_evo_enable()
2357 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_disable() local
2358 struct regmap *regmap = pll->clkr.regmap; in _alpha_pll_lucid_evo_disable()
2362 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in _alpha_pll_lucid_evo_disable()
2372 /* Disable the global PLL output */ in _alpha_pll_lucid_evo_disable()
2373 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in _alpha_pll_lucid_evo_disable()
2377 /* Disable the PLL outputs */ in _alpha_pll_lucid_evo_disable()
2378 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in _alpha_pll_lucid_evo_disable()
2382 /* Place the PLL mode in STANDBY */ in _alpha_pll_lucid_evo_disable()
2383 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in _alpha_pll_lucid_evo_disable()
2386 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); in _alpha_pll_lucid_evo_disable()
2391 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_prepare() local
2397 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in _alpha_pll_lucid_evo_prepare()
2437 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_recalc_rate() local
2438 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_recalc_rate()
2441 regmap_read(regmap, PLL_L_VAL(pll), &l); in alpha_pll_lucid_evo_recalc_rate()
2443 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); in alpha_pll_lucid_evo_recalc_rate()
2445 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); in alpha_pll_lucid_evo_recalc_rate()
2492 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_rivian_evo_pll_configure() argument
2495 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_rivian_evo_pll_configure()
2496 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_rivian_evo_pll_configure()
2497 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_rivian_evo_pll_configure()
2498 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_rivian_evo_pll_configure()
2499 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_rivian_evo_pll_configure()
2500 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_rivian_evo_pll_configure()
2501 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_rivian_evo_pll_configure()
2502 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_rivian_evo_pll_configure()
2504 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_rivian_evo_pll_configure()
2506 regmap_update_bits(regmap, PLL_MODE(pll), in clk_rivian_evo_pll_configure()
2515 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_recalc_rate() local
2518 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_rivian_evo_pll_recalc_rate()
2526 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_round_rate() local
2532 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_rivian_evo_pll_round_rate()
2535 min_freq = pll->vco_table[0].min_freq; in clk_rivian_evo_pll_round_rate()
2536 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_rivian_evo_pll_round_rate()
2550 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_stromer_pll_configure() argument
2555 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_stromer_pll_configure()
2556 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_stromer_pll_configure()
2557 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_stromer_pll_configure()
2559 if (pll_has_64bit_config(pll)) in clk_stromer_pll_configure()
2560 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_stromer_pll_configure()
2563 if (pll_alpha_width(pll) > 32) in clk_stromer_pll_configure()
2564 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_stromer_pll_configure()
2586 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_stromer_pll_configure()
2588 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ in clk_stromer_pll_configure()
2595 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); in clk_stromer_pll_configure()
2596 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_stromer_pll_configure()
2597 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_stromer_pll_configure()
2599 if (pll->flags & SUPPORTS_FSM_MODE) in clk_stromer_pll_configure()
2600 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_stromer_pll_configure()
2619 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_set_rate() local
2626 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_set_rate()
2629 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_set_rate()
2630 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_set_rate()
2633 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_set_rate()
2640 * Stromer PLL supports Dynamic programming. in clk_alpha_pll_stromer_set_rate()
2641 * It allows the PLL frequency to be changed on-the-fly without first in clk_alpha_pll_stromer_set_rate()
2644 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in clk_alpha_pll_stromer_set_rate()
2647 ret = wait_for_pll_update(pll); in clk_alpha_pll_stromer_set_rate()
2651 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_set_rate()
2668 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_plus_set_rate() local
2669 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_stromer_plus_set_rate()
2675 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); in clk_alpha_pll_stromer_plus_set_rate()
2679 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); in clk_alpha_pll_stromer_plus_set_rate()
2684 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_plus_set_rate()
2689 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_plus_set_rate()
2690 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_plus_set_rate()
2693 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_plus_set_rate()
2696 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); in clk_alpha_pll_stromer_plus_set_rate()
2700 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, in clk_alpha_pll_stromer_plus_set_rate()
2706 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_plus_set_rate()
2708 pr_err("Wait for PLL enable lock failed [%s] %d\n", in clk_alpha_pll_stromer_plus_set_rate()
2714 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, in clk_alpha_pll_stromer_plus_set_rate()
2730 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_regera_pll_configure() argument
2733 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_regera_pll_configure()
2734 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_regera_pll_configure()
2735 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_regera_pll_configure()
2736 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_regera_pll_configure()
2737 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_regera_pll_configure()
2738 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_regera_pll_configure()
2739 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_regera_pll_configure()
2740 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_regera_pll_configure()
2741 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_regera_pll_configure()
2742 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_regera_pll_configure()
2743 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_regera_pll_configure()
2746 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_regera_pll_configure()