Lines Matching +full:0 +full:x6040
36 { 249600000, 2000000000, 0 },
40 { 595200000UL, 3600000000UL, 0 },
44 .l = 0x3e,
45 .alpha = 0x8000,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002261,
48 .config_ctl_hi1_val = 0x329A699c,
49 .user_ctl_val = 0x00003100,
50 .user_ctl_hi_val = 0x00000805,
51 .user_ctl_hi1_val = 0x00000000,
55 .offset = 0x0,
72 { 0x1, 2 },
77 .offset = 0x0,
95 { 0x3, 3 },
100 .offset = 0x0,
118 .l = 0x1f,
119 .alpha = 0x4000,
120 .config_ctl_val = 0x20485699,
121 .config_ctl_hi_val = 0x00002261,
122 .config_ctl_hi1_val = 0x329A699c,
123 .user_ctl_val = 0x00000100,
124 .user_ctl_hi_val = 0x00000805,
125 .user_ctl_hi1_val = 0x00000000,
129 .offset = 0x1000,
146 { 0x1, 2 },
151 .offset = 0x1000,
169 .l = 0x4b,
170 .alpha = 0x0,
171 .config_ctl_val = 0x08200920,
172 .config_ctl_hi_val = 0x05002015,
173 .config_ctl_hi1_val = 0x00000000,
174 .user_ctl_val = 0x00000100,
175 .user_ctl_hi_val = 0x00000000,
176 .user_ctl_hi1_val = 0x00000000,
180 .offset = 0x2000,
197 { 0x1, 2 },
202 .offset = 0x2000,
220 .l = 0x24,
221 .alpha = 0x7555,
222 .config_ctl_val = 0x20485699,
223 .config_ctl_hi_val = 0x00002261,
224 .config_ctl_hi1_val = 0x329A699c,
225 .user_ctl_val = 0x00000100,
226 .user_ctl_hi_val = 0x00000805,
227 .user_ctl_hi1_val = 0x00000000,
231 .offset = 0x3000,
248 { 0x1, 2 },
253 .offset = 0x3000,
271 .l = 0x24,
272 .alpha = 0x7555,
273 .config_ctl_val = 0x20485699,
274 .config_ctl_hi_val = 0x00002261,
275 .config_ctl_hi1_val = 0x329A699c,
276 .user_ctl_val = 0x00000100,
277 .user_ctl_hi_val = 0x00000805,
278 .user_ctl_hi1_val = 0x00000000,
282 .offset = 0x4000,
299 { 0x1, 2 },
304 .offset = 0x4000,
322 { P_BI_TCXO, 0 },
338 { P_BI_TCXO, 0 },
348 { P_BI_TCXO, 0 },
358 { P_BI_TCXO, 0 },
368 { P_BI_TCXO, 0 },
378 { P_SLEEP_CLK, 0 },
386 { P_BI_TCXO, 0 },
394 F(19200000, P_BI_TCXO, 1, 0, 0),
395 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
396 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
397 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
398 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
399 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
404 .cmd_rcgr = 0x7010,
405 .mnd_width = 0,
419 F(19200000, P_BI_TCXO, 1, 0, 0),
420 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
421 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
426 .cmd_rcgr = 0xc0f8,
427 .mnd_width = 0,
441 F(19200000, P_BI_TCXO, 1, 0, 0),
442 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
447 .cmd_rcgr = 0xc0bc,
462 .cmd_rcgr = 0xc0d8,
477 F(19200000, P_BI_TCXO, 1, 0, 0),
478 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
483 .cmd_rcgr = 0xa068,
484 .mnd_width = 0,
498 F(19200000, P_BI_TCXO, 1, 0, 0),
499 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
504 .cmd_rcgr = 0x6000,
505 .mnd_width = 0,
519 .cmd_rcgr = 0x6020,
520 .mnd_width = 0,
534 .cmd_rcgr = 0x6040,
535 .mnd_width = 0,
549 .cmd_rcgr = 0x6060,
550 .mnd_width = 0,
564 .cmd_rcgr = 0x6080,
565 .mnd_width = 0,
579 .cmd_rcgr = 0x60a0,
580 .mnd_width = 0,
594 F(19200000, P_BI_TCXO, 1, 0, 0),
595 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
596 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
597 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
598 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
599 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
604 .cmd_rcgr = 0x703c,
605 .mnd_width = 0,
619 F(19200000, P_BI_TCXO, 1, 0, 0),
620 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
621 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
622 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
627 .cmd_rcgr = 0xc098,
628 .mnd_width = 0,
642 .cmd_rcgr = 0xc074,
643 .mnd_width = 0,
657 F(19200000, P_BI_TCXO, 1, 0, 0),
658 F(350000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
659 F(475000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
660 F(576000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
661 F(680000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
666 .cmd_rcgr = 0xa010,
667 .mnd_width = 0,
681 .reg = 0x9010,
682 .shift = 0,
696 F(19200000, P_BI_TCXO, 1, 0, 0),
697 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
698 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
703 .cmd_rcgr = 0xa040,
704 .mnd_width = 0,
718 F(19200000, P_BI_TCXO, 1, 0, 0),
719 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
720 F(475000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
721 F(576000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
722 F(680000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
727 .cmd_rcgr = 0xb010,
728 .mnd_width = 0,
742 .cmd_rcgr = 0xb040,
743 .mnd_width = 0,
757 F(19200000, P_BI_TCXO, 1, 0, 0),
758 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
759 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
764 .cmd_rcgr = 0xc000,
765 .mnd_width = 0,
779 .cmd_rcgr = 0xc01c,
780 .mnd_width = 0,
794 F(19200000, P_BI_TCXO, 1, 0, 0),
795 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
796 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
797 F(525000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
798 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
803 .cmd_rcgr = 0x8010,
804 .mnd_width = 0,
818 .cmd_rcgr = 0xc048,
819 .mnd_width = 0,
833 F(19200000, P_BI_TCXO, 1, 0, 0),
840 .cmd_rcgr = 0x5000,
855 .cmd_rcgr = 0x501c,
870 .cmd_rcgr = 0x5038,
885 .cmd_rcgr = 0x5054,
900 .cmd_rcgr = 0x5070,
915 .cmd_rcgr = 0x508c,
930 .cmd_rcgr = 0x50a8,
945 .cmd_rcgr = 0x901c,
946 .mnd_width = 0,
960 F(32768, P_SLEEP_CLK, 1, 0, 0),
965 .cmd_rcgr = 0xc170,
966 .mnd_width = 0,
980 F(19200000, P_BI_TCXO, 1, 0, 0),
981 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
986 .cmd_rcgr = 0x7058,
1001 F(19200000, P_BI_TCXO, 1, 0, 0),
1006 .cmd_rcgr = 0xc154,
1007 .mnd_width = 0,
1021 .halt_reg = 0x7070,
1024 .enable_reg = 0x7070,
1025 .enable_mask = BIT(0),
1039 .halt_reg = 0x7054,
1042 .enable_reg = 0x7054,
1043 .enable_mask = BIT(0),
1057 .halt_reg = 0x7038,
1060 .enable_reg = 0x7038,
1061 .enable_mask = BIT(0),
1075 .halt_reg = 0x7028,
1078 .enable_reg = 0x7028,
1079 .enable_mask = BIT(0),
1093 .halt_reg = 0xc114,
1096 .enable_reg = 0xc114,
1097 .enable_mask = BIT(0),
1111 .halt_reg = 0xc11c,
1114 .enable_reg = 0xc11c,
1115 .enable_mask = BIT(0),
1129 .halt_reg = 0xc0d4,
1132 .enable_reg = 0xc0d4,
1133 .enable_mask = BIT(0),
1147 .halt_reg = 0xc0f0,
1150 .enable_reg = 0xc0f0,
1151 .enable_mask = BIT(0),
1165 .halt_reg = 0xc150,
1168 .enable_reg = 0xc150,
1169 .enable_mask = BIT(0),
1183 .halt_reg = 0xc0f4,
1186 .enable_reg = 0xc0f4,
1187 .enable_mask = BIT(0),
1201 .halt_reg = 0x6018,
1204 .enable_reg = 0x6018,
1205 .enable_mask = BIT(0),
1219 .halt_reg = 0x6038,
1222 .enable_reg = 0x6038,
1223 .enable_mask = BIT(0),
1237 .halt_reg = 0x6058,
1240 .enable_reg = 0x6058,
1241 .enable_mask = BIT(0),
1255 .halt_reg = 0x6078,
1258 .enable_reg = 0x6078,
1259 .enable_mask = BIT(0),
1273 .halt_reg = 0x6098,
1276 .enable_reg = 0x6098,
1277 .enable_mask = BIT(0),
1291 .halt_reg = 0x60b8,
1294 .enable_reg = 0x60b8,
1295 .enable_mask = BIT(0),
1309 .halt_reg = 0x601c,
1312 .enable_reg = 0x601c,
1313 .enable_mask = BIT(0),
1327 .halt_reg = 0x603c,
1330 .enable_reg = 0x603c,
1331 .enable_mask = BIT(0),
1345 .halt_reg = 0x605c,
1348 .enable_reg = 0x605c,
1349 .enable_mask = BIT(0),
1363 .halt_reg = 0x607c,
1366 .enable_reg = 0x607c,
1367 .enable_mask = BIT(0),
1381 .halt_reg = 0x609c,
1384 .enable_reg = 0x609c,
1385 .enable_mask = BIT(0),
1399 .halt_reg = 0x60bc,
1402 .enable_reg = 0x60bc,
1403 .enable_mask = BIT(0),
1417 .halt_reg = 0xc0b0,
1420 .enable_reg = 0xc0b0,
1421 .enable_mask = BIT(0),
1435 .halt_reg = 0xc0b8,
1438 .enable_reg = 0xc0b8,
1439 .enable_mask = BIT(0),
1453 .halt_reg = 0xc16c,
1456 .enable_reg = 0xc16c,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0xc094,
1474 .enable_reg = 0xc094,
1475 .enable_mask = BIT(0),
1489 .halt_reg = 0xc08c,
1492 .enable_reg = 0xc08c,
1493 .enable_mask = BIT(0),
1507 .halt_reg = 0xa088,
1510 .enable_reg = 0xa088,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0xa030,
1528 .enable_reg = 0xa030,
1529 .enable_mask = BIT(0),
1543 .halt_reg = 0xa084,
1546 .enable_reg = 0xa084,
1547 .enable_mask = BIT(0),
1561 .halt_reg = 0xa028,
1564 .enable_reg = 0xa028,
1565 .enable_mask = BIT(0),
1579 .halt_reg = 0xa080,
1582 .enable_reg = 0xa080,
1583 .enable_mask = BIT(0),
1597 .halt_reg = 0xa058,
1600 .enable_reg = 0xa058,
1601 .enable_mask = BIT(0),
1615 .halt_reg = 0xa03c,
1618 .enable_reg = 0xa03c,
1619 .enable_mask = BIT(0),
1633 .halt_reg = 0xb068,
1636 .enable_reg = 0xb068,
1637 .enable_mask = BIT(0),
1651 .halt_reg = 0xb030,
1654 .enable_reg = 0xb030,
1655 .enable_mask = BIT(0),
1669 .halt_reg = 0xb064,
1672 .enable_reg = 0xb064,
1673 .enable_mask = BIT(0),
1687 .halt_reg = 0xb028,
1690 .enable_reg = 0xb028,
1691 .enable_mask = BIT(0),
1705 .halt_reg = 0xb060,
1708 .enable_reg = 0xb060,
1709 .enable_mask = BIT(0),
1723 .halt_reg = 0xb058,
1726 .enable_reg = 0xb058,
1727 .enable_mask = BIT(0),
1741 .halt_reg = 0xb03c,
1744 .enable_reg = 0xb03c,
1745 .enable_mask = BIT(0),
1759 .halt_reg = 0xc040,
1762 .enable_reg = 0xc040,
1763 .enable_mask = BIT(0),
1777 .halt_reg = 0xc044,
1780 .enable_reg = 0xc044,
1781 .enable_mask = BIT(0),
1795 .halt_reg = 0xc018,
1798 .enable_reg = 0xc018,
1799 .enable_mask = BIT(0),
1813 .halt_reg = 0xc03c,
1816 .enable_reg = 0xc03c,
1817 .enable_mask = BIT(0),
1831 .halt_reg = 0xc034,
1834 .enable_reg = 0xc034,
1835 .enable_mask = BIT(0),
1849 .halt_reg = 0x8040,
1852 .enable_reg = 0x8040,
1853 .enable_mask = BIT(0),
1867 .halt_reg = 0x803c,
1870 .enable_reg = 0x803c,
1871 .enable_mask = BIT(0),
1885 .halt_reg = 0x8038,
1888 .enable_reg = 0x8038,
1889 .enable_mask = BIT(0),
1903 .halt_reg = 0x8028,
1906 .enable_reg = 0x8028,
1907 .enable_mask = BIT(0),
1921 .halt_reg = 0xc060,
1924 .enable_reg = 0xc060,
1925 .enable_mask = BIT(0),
1939 .halt_reg = 0x5018,
1942 .enable_reg = 0x5018,
1943 .enable_mask = BIT(0),
1957 .halt_reg = 0x5034,
1960 .enable_reg = 0x5034,
1961 .enable_mask = BIT(0),
1975 .halt_reg = 0x5050,
1978 .enable_reg = 0x5050,
1979 .enable_mask = BIT(0),
1993 .halt_reg = 0x506c,
1996 .enable_reg = 0x506c,
1997 .enable_mask = BIT(0),
2011 .halt_reg = 0x5088,
2014 .enable_reg = 0x5088,
2015 .enable_mask = BIT(0),
2029 .halt_reg = 0x50a4,
2032 .enable_reg = 0x50a4,
2033 .enable_mask = BIT(0),
2047 .halt_reg = 0x50c0,
2050 .enable_reg = 0x50c0,
2051 .enable_mask = BIT(0),
2065 .halt_reg = 0x9040,
2068 .enable_reg = 0x9040,
2069 .enable_mask = BIT(0),
2083 .halt_reg = 0x903c,
2086 .enable_reg = 0x903c,
2087 .enable_mask = BIT(0),
2101 .halt_reg = 0x9014,
2104 .enable_reg = 0x9014,
2105 .enable_mask = BIT(0),
2119 .halt_reg = 0x9038,
2122 .enable_reg = 0x9038,
2123 .enable_mask = BIT(0),
2137 .halt_reg = 0x9034,
2140 .enable_reg = 0x9034,
2141 .enable_mask = BIT(0),
2155 .halt_reg = 0x9044,
2158 .enable_reg = 0x9044,
2159 .enable_mask = BIT(0),
2173 .halt_reg = 0x9048,
2176 .enable_reg = 0x9048,
2177 .enable_mask = BIT(0),
2191 .halt_reg = 0xc188,
2194 .enable_reg = 0xc188,
2195 .enable_mask = BIT(0),
2211 .gdscr = 0x7004,
2220 .gdscr = 0x8004,
2229 .gdscr = 0x9004,
2238 .gdscr = 0xa004,
2248 .gdscr = 0xb004,
2258 .gdscr = 0xc144,
2390 [CAM_CC_BPS_BCR] = { 0x7000 },
2391 [CAM_CC_ICP_BCR] = { 0xc070 },
2392 [CAM_CC_IFE_0_BCR] = { 0xa000 },
2393 [CAM_CC_IFE_1_BCR] = { 0xb000 },
2394 [CAM_CC_IPE_0_BCR] = { 0x8000 },
2395 [CAM_CC_SBI_BCR] = { 0x9000 },
2402 .max_register = 0xe004,