Lines Matching +full:0 +full:x6040
43 { 600000000, 3300000000, 0 },
47 { 249600000, 2000000000, 0 },
51 .l = 0x3e,
52 .alpha = 0x8000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00002267,
55 .config_ctl_hi1_val = 0x00000024,
56 .test_ctl_val = 0x00000000,
57 .test_ctl_hi_val = 0x00000000,
58 .test_ctl_hi1_val = 0x00000020,
59 .user_ctl_val = 0x00003100,
60 .user_ctl_hi_val = 0x00000805,
61 .user_ctl_hi1_val = 0x000000D0,
65 .offset = 0x0,
82 { 0x1, 2 },
87 .offset = 0x0,
105 { 0x3, 3 },
110 .offset = 0x0,
128 .l = 0x1f,
129 .alpha = 0x4000,
130 .config_ctl_val = 0x20485699,
131 .config_ctl_hi_val = 0x00002267,
132 .config_ctl_hi1_val = 0x00000024,
133 .test_ctl_val = 0x00000000,
134 .test_ctl_hi_val = 0x00000000,
135 .test_ctl_hi1_val = 0x00000020,
136 .user_ctl_val = 0x00000100,
137 .user_ctl_hi_val = 0x00000805,
138 .user_ctl_hi1_val = 0x000000D0,
142 .offset = 0x1000,
159 { 0x1, 2 },
164 .offset = 0x1000,
182 .l = 0x32,
183 .alpha = 0x0,
184 .config_ctl_val = 0x10000807,
185 .config_ctl_hi_val = 0x00000011,
186 .config_ctl_hi1_val = 0x04300142,
187 .test_ctl_val = 0x04000400,
188 .test_ctl_hi_val = 0x00004000,
189 .test_ctl_hi1_val = 0x00000000,
190 .user_ctl_val = 0x00000100,
191 .user_ctl_hi_val = 0x00000000,
192 .user_ctl_hi1_val = 0x00000000,
196 .offset = 0x2000,
213 { 0x1, 2 },
218 .offset = 0x2000,
236 .l = 0x29,
237 .alpha = 0xaaaa,
238 .config_ctl_val = 0x20485699,
239 .config_ctl_hi_val = 0x00002267,
240 .config_ctl_hi1_val = 0x00000024,
241 .test_ctl_val = 0x00000000,
242 .test_ctl_hi_val = 0x00000000,
243 .test_ctl_hi1_val = 0x00000020,
244 .user_ctl_val = 0x00000100,
245 .user_ctl_hi_val = 0x00000805,
246 .user_ctl_hi1_val = 0x000000D0,
250 .offset = 0x3000,
267 { 0x1, 2 },
272 .offset = 0x3000,
290 .l = 0x29,
291 .alpha = 0xaaaa,
292 .config_ctl_val = 0x20485699,
293 .config_ctl_hi_val = 0x00002267,
294 .config_ctl_hi1_val = 0x00000024,
295 .test_ctl_val = 0x00000000,
296 .test_ctl_hi_val = 0x00000000,
297 .test_ctl_hi1_val = 0x00000020,
298 .user_ctl_val = 0x00000100,
299 .user_ctl_hi_val = 0x00000805,
300 .user_ctl_hi1_val = 0x000000D0,
304 .offset = 0x4000,
321 { 0x1, 2 },
326 .offset = 0x4000,
344 { P_BI_TCXO, 0 },
360 { P_BI_TCXO, 0 },
370 { P_BI_TCXO, 0 },
380 { P_BI_TCXO, 0 },
390 { P_BI_TCXO, 0 },
400 F(19200000, P_BI_TCXO, 1, 0, 0),
401 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
402 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
403 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
404 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
405 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
410 .cmd_rcgr = 0x7010,
411 .mnd_width = 0,
425 F(19200000, P_BI_TCXO, 1, 0, 0),
426 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
427 F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0),
428 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
429 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
430 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
435 .cmd_rcgr = 0xc170,
436 .mnd_width = 0,
450 F(19200000, P_BI_TCXO, 1, 0, 0),
451 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
456 .cmd_rcgr = 0xc108,
471 .cmd_rcgr = 0xc124,
486 F(19200000, P_BI_TCXO, 1, 0, 0),
487 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
492 .cmd_rcgr = 0xa064,
493 .mnd_width = 0,
507 F(19200000, P_BI_TCXO, 1, 0, 0),
508 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
513 .cmd_rcgr = 0x6004,
514 .mnd_width = 0,
528 .cmd_rcgr = 0x6028,
529 .mnd_width = 0,
543 .cmd_rcgr = 0x604c,
544 .mnd_width = 0,
558 .cmd_rcgr = 0x6070,
559 .mnd_width = 0,
573 F(19200000, P_BI_TCXO, 1, 0, 0),
574 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
575 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
576 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
577 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
578 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
583 .cmd_rcgr = 0x703c,
584 .mnd_width = 0,
598 F(19200000, P_BI_TCXO, 1, 0, 0),
599 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
600 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
601 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
606 .cmd_rcgr = 0xc0e0,
607 .mnd_width = 0,
621 F(19200000, P_BI_TCXO, 1, 0, 0),
622 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
623 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
628 .cmd_rcgr = 0xc0b8,
629 .mnd_width = 0,
643 F(19200000, P_BI_TCXO, 1, 0, 0),
644 F(400000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
645 F(558000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
646 F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
647 F(847000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
648 F(950000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
653 .cmd_rcgr = 0xa010,
654 .mnd_width = 0,
668 F(19200000, P_BI_TCXO, 1, 0, 0),
669 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
670 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
671 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
672 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
677 .cmd_rcgr = 0xa03c,
678 .mnd_width = 0,
692 F(19200000, P_BI_TCXO, 1, 0, 0),
693 F(400000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
694 F(558000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
695 F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
696 F(847000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
697 F(950000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
702 .cmd_rcgr = 0xb010,
703 .mnd_width = 0,
717 .cmd_rcgr = 0xb034,
718 .mnd_width = 0,
732 F(19200000, P_BI_TCXO, 1, 0, 0),
733 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
734 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
735 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
736 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
741 .cmd_rcgr = 0xc004,
742 .mnd_width = 0,
756 .cmd_rcgr = 0xc020,
757 .mnd_width = 0,
771 .cmd_rcgr = 0xc048,
772 .mnd_width = 0,
786 .cmd_rcgr = 0xc064,
787 .mnd_width = 0,
801 F(19200000, P_BI_TCXO, 1, 0, 0),
802 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
803 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
804 F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
805 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
810 .cmd_rcgr = 0x8010,
811 .mnd_width = 0,
825 .cmd_rcgr = 0xc08c,
826 .mnd_width = 0,
840 F(19200000, P_BI_TCXO, 1, 0, 0),
841 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
842 F(240000000, P_CAM_CC_PLL2_OUT_MAIN, 2, 0, 0),
843 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
844 F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
845 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
850 .cmd_rcgr = 0xc144,
851 .mnd_width = 0,
866 F(19200000, P_BI_TCXO, 1, 0, 0),
868 F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 14, 0, 0),
873 .cmd_rcgr = 0x5004,
888 .cmd_rcgr = 0x5024,
903 .cmd_rcgr = 0x5044,
918 .cmd_rcgr = 0x5064,
933 F(19200000, P_BI_TCXO, 1, 0, 0),
934 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
939 .cmd_rcgr = 0x7058,
954 .halt_reg = 0x7070,
957 .enable_reg = 0x7070,
958 .enable_mask = BIT(0),
972 .halt_reg = 0x7054,
975 .enable_reg = 0x7054,
976 .enable_mask = BIT(0),
990 .halt_reg = 0x7038,
993 .enable_reg = 0x7038,
994 .enable_mask = BIT(0),
1008 .halt_reg = 0x7028,
1011 .enable_reg = 0x7028,
1012 .enable_mask = BIT(0),
1026 .halt_reg = 0xc18c,
1029 .enable_reg = 0xc18c,
1030 .enable_mask = BIT(0),
1044 .halt_reg = 0xc194,
1047 .enable_reg = 0xc194,
1048 .enable_mask = BIT(0),
1057 .halt_reg = 0xc120,
1060 .enable_reg = 0xc120,
1061 .enable_mask = BIT(0),
1075 .halt_reg = 0xc13c,
1078 .enable_reg = 0xc13c,
1079 .enable_mask = BIT(0),
1093 .halt_reg = 0xc1c8,
1096 .enable_reg = 0xc1c8,
1097 .enable_mask = BIT(0),
1111 .halt_reg = 0xc168,
1114 .enable_reg = 0xc168,
1115 .enable_mask = BIT(0),
1129 .halt_reg = 0x601c,
1132 .enable_reg = 0x601c,
1133 .enable_mask = BIT(0),
1147 .halt_reg = 0x6040,
1150 .enable_reg = 0x6040,
1151 .enable_mask = BIT(0),
1165 .halt_reg = 0x6064,
1168 .enable_reg = 0x6064,
1169 .enable_mask = BIT(0),
1183 .halt_reg = 0x6088,
1186 .enable_reg = 0x6088,
1187 .enable_mask = BIT(0),
1201 .halt_reg = 0x6020,
1204 .enable_reg = 0x6020,
1205 .enable_mask = BIT(0),
1219 .halt_reg = 0x6044,
1222 .enable_reg = 0x6044,
1223 .enable_mask = BIT(0),
1237 .halt_reg = 0x6068,
1240 .enable_reg = 0x6068,
1241 .enable_mask = BIT(0),
1255 .halt_reg = 0x608c,
1258 .enable_reg = 0x608c,
1259 .enable_mask = BIT(0),
1273 .halt_reg = 0xc0f8,
1276 .enable_reg = 0xc0f8,
1277 .enable_mask = BIT(0),
1291 .halt_reg = 0xc100,
1294 .enable_reg = 0xc100,
1295 .enable_mask = BIT(0),
1309 .halt_reg = 0xc0d8,
1312 .enable_reg = 0xc0d8,
1313 .enable_mask = BIT(0),
1327 .halt_reg = 0xc0d0,
1330 .enable_reg = 0xc0d0,
1331 .enable_mask = BIT(0),
1345 .halt_reg = 0xa080,
1348 .enable_reg = 0xa080,
1349 .enable_mask = BIT(0),
1363 .halt_reg = 0xa028,
1366 .enable_reg = 0xa028,
1367 .enable_mask = BIT(0),
1381 .halt_reg = 0xa07c,
1384 .enable_reg = 0xa07c,
1385 .enable_mask = BIT(0),
1399 .halt_reg = 0xa054,
1402 .enable_reg = 0xa054,
1403 .enable_mask = BIT(0),
1417 .halt_reg = 0xa038,
1420 .enable_reg = 0xa038,
1421 .enable_mask = BIT(0),
1435 .halt_reg = 0xb058,
1438 .enable_reg = 0xb058,
1439 .enable_mask = BIT(0),
1453 .halt_reg = 0xb028,
1456 .enable_reg = 0xb028,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0xb054,
1474 .enable_reg = 0xb054,
1475 .enable_mask = BIT(0),
1489 .halt_reg = 0xb04c,
1492 .enable_reg = 0xb04c,
1493 .enable_mask = BIT(0),
1507 .halt_reg = 0xb030,
1510 .enable_reg = 0xb030,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0xc01c,
1528 .enable_reg = 0xc01c,
1529 .enable_mask = BIT(0),
1543 .halt_reg = 0xc040,
1546 .enable_reg = 0xc040,
1547 .enable_mask = BIT(0),
1561 .halt_reg = 0xc038,
1564 .enable_reg = 0xc038,
1565 .enable_mask = BIT(0),
1579 .halt_reg = 0xc060,
1582 .enable_reg = 0xc060,
1583 .enable_mask = BIT(0),
1597 .halt_reg = 0xc084,
1600 .enable_reg = 0xc084,
1601 .enable_mask = BIT(0),
1615 .halt_reg = 0xc07c,
1618 .enable_reg = 0xc07c,
1619 .enable_mask = BIT(0),
1633 .halt_reg = 0x8040,
1636 .enable_reg = 0x8040,
1637 .enable_mask = BIT(0),
1651 .halt_reg = 0x803c,
1654 .enable_reg = 0x803c,
1655 .enable_mask = BIT(0),
1669 .halt_reg = 0x8038,
1672 .enable_reg = 0x8038,
1673 .enable_mask = BIT(0),
1687 .halt_reg = 0x8028,
1690 .enable_reg = 0x8028,
1691 .enable_mask = BIT(0),
1705 .halt_reg = 0x9028,
1708 .enable_reg = 0x9028,
1709 .enable_mask = BIT(0),
1723 .halt_reg = 0x9024,
1726 .enable_reg = 0x9024,
1727 .enable_mask = BIT(0),
1741 .halt_reg = 0x9020,
1744 .enable_reg = 0x9020,
1745 .enable_mask = BIT(0),
1759 .halt_reg = 0x9010,
1762 .enable_reg = 0x9010,
1763 .enable_mask = BIT(0),
1777 .halt_reg = 0xc0a4,
1780 .enable_reg = 0xc0a4,
1781 .enable_mask = BIT(0),
1795 .halt_reg = 0xc15c,
1798 .enable_reg = 0xc15c,
1799 .enable_mask = BIT(0),
1813 .halt_reg = 0x501c,
1816 .enable_reg = 0x501c,
1817 .enable_mask = BIT(0),
1831 .halt_reg = 0x503c,
1834 .enable_reg = 0x503c,
1835 .enable_mask = BIT(0),
1849 .halt_reg = 0x505c,
1852 .enable_reg = 0x505c,
1853 .enable_mask = BIT(0),
1867 .halt_reg = 0x507c,
1870 .enable_reg = 0x507c,
1871 .enable_mask = BIT(0),
1885 .gdscr = 0xc1bc,
1886 .en_rest_wait_val = 0x2,
1887 .en_few_wait_val = 0x2,
1888 .clk_dis_wait_val = 0xf,
1897 .gdscr = 0x7004,
1898 .en_rest_wait_val = 0x2,
1899 .en_few_wait_val = 0x2,
1900 .clk_dis_wait_val = 0xf,
1910 .gdscr = 0xa004,
1911 .en_rest_wait_val = 0x2,
1912 .en_few_wait_val = 0x2,
1913 .clk_dis_wait_val = 0xf,
1923 .gdscr = 0xb004,
1924 .en_rest_wait_val = 0x2,
1925 .en_few_wait_val = 0x2,
1926 .clk_dis_wait_val = 0xf,
1936 .gdscr = 0x8004,
1937 .en_rest_wait_val = 0x2,
1938 .en_few_wait_val = 0x2,
1939 .clk_dis_wait_val = 0xf,
1949 .gdscr = 0x9004,
1950 .en_rest_wait_val = 0x2,
1951 .en_few_wait_val = 0x2,
1952 .clk_dis_wait_val = 0xf,
2065 [CAM_CC_BPS_BCR] = { 0x7000 },
2066 [CAM_CC_CAMNOC_BCR] = { 0xc16c },
2067 [CAM_CC_CCI_BCR] = { 0xc104 },
2068 [CAM_CC_CPAS_BCR] = { 0xc164 },
2069 [CAM_CC_CSI0PHY_BCR] = { 0x6000 },
2070 [CAM_CC_CSI1PHY_BCR] = { 0x6024 },
2071 [CAM_CC_CSI2PHY_BCR] = { 0x6048 },
2072 [CAM_CC_CSI3PHY_BCR] = { 0x606c },
2073 [CAM_CC_FD_BCR] = { 0xc0dc },
2074 [CAM_CC_ICP_BCR] = { 0xc0b4 },
2075 [CAM_CC_IFE_0_BCR] = { 0xa000 },
2076 [CAM_CC_IFE_1_BCR] = { 0xb000 },
2077 [CAM_CC_IFE_LITE_0_BCR] = { 0xc000 },
2078 [CAM_CC_IFE_LITE_1_BCR] = { 0xc044 },
2079 [CAM_CC_IPE_0_BCR] = { 0x8000 },
2080 [CAM_CC_IPE_1_BCR] = { 0x9000 },
2081 [CAM_CC_JPEG_BCR] = { 0xc088 },
2082 [CAM_CC_LRME_BCR] = { 0xc140 },
2083 [CAM_CC_MCLK0_BCR] = { 0x5000 },
2084 [CAM_CC_MCLK1_BCR] = { 0x5020 },
2085 [CAM_CC_MCLK2_BCR] = { 0x5040 },
2086 [CAM_CC_MCLK3_BCR] = { 0x5060 },
2093 .max_register = 0xe004,
2139 qcom_branch_set_clk_en(regmap, 0xc1e4); /* cam_cc_gdsc_clk */ in cam_cc_sm8150_probe()